ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 111

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
11.4.4
Slave mode
Note:
Functional description
Refer to the CR, SR1 and SR2 registers in
By default the I
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the general call
address (if selected by software).
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
●
●
●
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 57
Next, in 7-bit mode read the DR register to determine from the least significant bit (data
direction bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
●
●
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see
When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an
interrupt if the ITE bit is set.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if
the ACK bit is set.
Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
–
–
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
transfer sequencing EV1).
2
C interface operates in Slave mode (M/SL bit is cleared) except when it
Figure 57
Doc ID 13562 Rev 3
Figure 57
Transfer sequencing EV3).
Transfer sequencing EV2).
Section
11.4.7. for the bit definitions.
On-chip peripherals
111/188