ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 150

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

Electrical characteristics
13.4.2
13.5
13.5.1
150/188
On-chip peripherals
Table 68.
1. Data based on a differential I
2. Data based on a differential I
3. Data based on a differential I
Communication interface characteristics
I
Subject to general operating conditions for V
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI). The ST7 I
requirements of the Standard I
T
Table 69.
1. The I
Table 70
SCL line frequency.
I
2
Symbol
Symbol
A
I
DD(ADC)
I
f
DD(I2C)
C interface
DD(AT)
SCL
= -40 °C to 125 °C, unless otherwise specified.
running in PWM mode at f
I
toggling consumption (4.7 kOhm external pull-up on clock and data lines).
conversions with amplifier disabled.
2
C master communication at 100 kHz (data sent equal to 55h). This measurement include the pad
(1)
2
C interface will not function below the minimum clock speed of 4 MHz (see
gives the values to be written in the I2CCCR register to obtain the required I
12-bit auto-reload timer supply current
ADC supply current when converting
On-chip peripheral characteristics
I
2
C interface characteristics
I²C SCL frequency
Parameter
I
2
C supply current
cpu
Parameter
DD
DD
DD
= 8 MHz.
measurement between reset configuration (I
measurement between reset configuration (timer stopped) and a timer
measurement between reset configuration and continuous A/D
Doc ID 13562 Rev 3
2
C communication protocol.
(2)
f
CPU
2
C interface meets the electrical and timing
V
DD
(3)
DD
(1)
=4 MHz to 8 MHz,
, f
Conditions
= 2.4 to 5.5 V
OSC
f
f
f
f
f
CPU
CPU
CPU
CPU
ADC
, and T
=4 MHz
=8 MHz
=4 MHz
=8 MHz
=4 MHz
Conditions
A
unless otherwise specified.
2
C disabled) and a permanent
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
Table
=3.0 V
=5.0 V
=3.0 V
=5.0 V
=3.0 V
=5.0 V
Min
70).
ST7LITE49M
1000
Typ
600
400
600
Max
400
10
50
2
Unit
C
μA
μA
μA
Unit
kHz