ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 113

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
Master mode
Note:
Note:
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
The master then waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see
EV5).
Slave address transmission
1.
2.
3.
4.
5.
6.
In 10-bit addressing mode, to switch the master to receiver mode, software must generate a
repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●
●
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
The slave address is then sent to the SDA line via the internal shift register.
–
–
The master then waits for a read of the SR1 register followed by a write in the DR
register, holding the SCL line low (see
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set),
the EVF bit is set by hardware with interrupt generation if the ITE bit is set.
The master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see
EV6).
Next the master must enter receiver or transmitter mode.
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event. The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Doc ID 13562 Rev 3
Figure 57
transfer sequencing EV7).
Figure 57
transfer sequencing EV9).
Figure 57
Figure 57
Transfer sequencing
On-chip peripherals
transfer sequencing
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