ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 121

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
Note:
I
Reset value: 0000 0000 (00h)
Bits 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure bit
Bit 3 = STOPF Stop detection bit (slave mode)
Bit 2 = ARLO Arbitration lost bit
In a Multimaster environment, when the interface is configured in master receive mode it
does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the
ARLO bit from the I2CSR2 register may occur when a second master simultaneously
requests the same data from the same slave and the I
data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error bit
2
C status register 2 (I2CSR2)
This bit is set by hardware when no acknowledge is returned. An interrupt is generated
if ITE=1. It is cleared by software reading SR2 register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at
the same time.
0: No acknowledge failure
1: Acknowledge failure
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
This bit is set by hardware when the interface loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
7
0
0
0
Doc ID 13562 Rev 3
AF
Read Only
STOPF
2
C master does not acknowledge the
ARLO
On-chip peripherals
BERR
GCAL
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