ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 96

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
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Bit 6 = BREDGE Break input edge selection bit
Bit 5 = BA Break active bit
Bit 4 = BPEN Break pin enable bit
Bits 3:0 = PWM[3:0] Break pattern bits
PWMx duty cycle register High (DCRxH)
Reset value: 0000 0000 (00h)
Bits 15:12 = Reserved.
PWMx duty cycle register Low (DCRxL)
Reset value: 0000 0000 (00h)
Bits 11:0 = DCRx[11:0] PWMx duty cycle value: this 12-bit value is written by software. It
defines the duty cycle of the corresponding PWM output signal (see
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWMx output signal (see
be compared with the 12-bit upcounter value.
DCR7
15
This bit is read/write by software and cleared by hardware after reset. It selects the
active level of Break signal.
0: Low level of Break selected as active level
1: High level of Break selected as active level
This bit is read/write by software, cleared by hardware after reset and set by hardware
when the active level defined by the BR1EDGE bit is applied on the BREAK pin. It
activates/deactivates the Break function.
0: Break not active
1: Break active
This bit is read/write by software and cleared by hardware after reset.
0: Break pin disabled
1: Break pin enabled
These bits are read/write by software and cleared by hardware after a reset. They are
used to force the four PWMx output signals into a stable state when the Break function
is active and corresponding OEx bit is set.
0
7
DCR6
0
DCR5
0
Figure
Doc ID 13562 Rev 3
40). In output compare mode, they define the value to
DCR4
0
Read/write
Read/write
DCR11
DCR3
DCR10
DCR2
Figure
DCR1
DCR9
40).
ST7LITE49M
DCR0
DCR8
0
8