TMP92xy22FG Toshiba, TMP92xy22FG Datasheet
TMP92xy22FG
Specifications of TMP92xy22FG
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TMP92xy22FG Summary of contents
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... TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Preface ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any parties ...
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External memory expansion • Expandable Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ･･･Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output: 4 channels (6) ...
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PG0 to PG7 (AN0 to AN7) PG3 ( ) ADTRG 10-bit 8-ch AVCC AD AVSS converter VREFH VREFL PF0 (TXD0) Serial I/O PF1 (RXD0) SIO0 PF2 (SCLK0/ ) CTS0 PF3 (TXD1) Serial I/O PF4 (RXD1) SIO1 PF5 (SCLK1/ ) CTS1 ...
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Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. VREFL 1 VREFH PG0/AN0 PG1/AN1 PG2/AN2 5 PG3/AN3/ ...
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Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Number Pin Names I/O of Pins I/O P10 to P17 I/O 8 ...
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Table 2.2.2 Pin Names and Functions (2/2) Number Pin Names I/O of Pins PC0 I/O 1 TA0IN Input PC1 I/O INT1 1 Input TA1OUT Output PC3 I/O 1 INT0 Input PC5 I/O INT2 1 Input TA3OUT Output PC6 I/O INT3 ...
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Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this ...
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Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system ...
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V 3 RESET Oscillator operation time + 20 system clocks Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to ...
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Memory Map Figure 3.2.1 shows memory map of TMP92CM22. 000000H 000100H 001FE0H 002000H 00A000H 010000H F00000H F10000H FFFF00H Vector table (256 bytes) FFFFFFH Note 1: When use emulator, optional 64 Kbytes of 16-Mbyte area are used to control emulator. ...
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Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 ...
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The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Instruction IDLE2 mode Interrupt (I/O operation) Instruction IDLE1 mode ...
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Block Diagram of System Clock SYSCR2<WUPTM1:0> PLLCR<PLUPFG> Warm-up timer (for high-frequency f PLL PLLCR<PLLON> PLL (Clock doubler) High- X1 frequency X2 f oscillator OSCH f SYS TMRA0 to TMRA3 and f TMRB0 to TMRB1 iO φT0 SIO0 and SIO1 ...
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SFRs 7 − SYSCR0 Bit symbol (10E0H) Read/Write R/W After reset 1 Function Always write “1”. SYSCR1 Bit symbol (10E1H) Read/Write After reset Function − SYSCR2 Bit symbol (10E2H) Read/Write R/W After reset 0 Function Always write “0”. Note: ...
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Bit symbol PLLON PLLCR (10E8H) Read/Write R/W After reset Function 0: PLL stop PLL run Note: Logic of PLLCR<LWUPFG> is different DFM of 900/L1. 7 Bit symbol PROTECT EMCCR0 (10E3H) Read/Write ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/ used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1<GEAR2:0>, SYSCR1<GEAR2:0> sets the high-frequency clock gear to ...
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Clock Doubler (PLL) PLL outputs the f PLL PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. Note 1: Input frequency ...
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Example 2: PLL stopping PLLCR EQU Don’t care <FCSEL> <PLLON> PLL output: f PLL System clock f SYS Changes from 40 MHz to 10 MHz. Limitation point on the use of PLL 1. When PLL is started, ...
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Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency ...
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Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) X1 pin X2 pin (Setting method) The oscillator is disabled and starts ...
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Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by ...
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Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: ...
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How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. ...
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Table 3.3.3 Source of Halt State Release and Halt Release Operation Status of Received Interrupt HALT Mode NMI INTWDT INT0 to 3 (Note1) INT4 to 5 INTTA0 to 3, INTTB00, 01, 10, 11, O0, O1 INTRX0 to 1, TX0 to ...
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Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDRV, DRVE> register. Table 3.3.5, Table 3.3.6 shows the state of these pins ...
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Input Port Function During Name Name Reset Used as D0-D7 D0-D7 P10-P17 D8-D15 OFF − P40-P47 − P50-P57 − P60-P67 P76 WAIT P90 SCK P91 SDA SI P92 SCL − PA0-PA7(*1) PC0 TA0IN PC1 INT1 PC3 INT0 PC5 INT2 PC6 ...
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When the CPU is Output Port Function During Name When Name Reset Used as Function ON upon D0-D7 D0-D7 OFF external P10-P17 D8-D15 read P40-P47 A0-A7 P50-P57 A8-A15 P60-P67 A16-A23 P70 RD P71 WRLL ON P72 WRLU P73 WRUL P74 ...
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Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller. The TMP92CM22 has a total of 41 interrupts divided into the following types: Interrupts generated by CPU: 9 sources (Software ...
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Interrupt processing Interrupt specified by micro DMA start vector? Interrupt vector “V” read Interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> ← Level of INTNEST ← PC←(FFFF00H Interrupt process program RETI instruction POP SR ...
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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L, TLCS-900/H, and TLCS-900/L1. (1) The CPU reads the interrupt vector from the interrupt controller. If ...
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Table 3.4.1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Default Priority Type 1 Reset or “SWI0” instruction 2 “SWI1” instruction 3 “Illegal instruction” or “SWI2” instruction 4 “SWI3” instruction 5 Non- “SWI4” instruction maskable 6 “SWI5” instruction 7 “SWI6” ...
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Default Priority Type 52 INTAD: AD conversion end 53 INTTC0: Micro DMA end (Channel 0) 54 INTTC1: Micro DMA end (Channel 1) 55 INTTC2: Micro DMA end (Channel 2) 56 INTTC3: Micro DMA end (Channel 3) Maskable 57 INTTC4: Micro ...
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Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless ...
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Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to ...
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Detailed description of the transfer mode register Mode DMAM0 to DMAM7 DMAM [4:0] Destination address INC mode 000 zz (DMADn +) ← (DMASn) ← DMACn − 1 DMACn If DMACn = 0 then INTTC Source address ...
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Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Figure 3.4.3 Block Diagram of Interrupt Controller 92CM22-39 TMP92CM22 2007-02-16 ...
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Interrupt priority setting registers Symbol Name Address INT1&INT2 INTE12 D0H enable INT3 INTE3 D1H enable INTTA0& INTETA01 INTTA1 D4H enable INTTA2& INTTA3 INTETA23 D5H enable INTTB00& INTETB0 INTTB01 D8H enable INTTBO0 INTETBO0 (Overflow) DAH enable INTRX0& INTES0 INTTX0 DBH ...
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Symbol Name Address INT0&INTAD INTE0AD F0H enable INTTC0& INTETC01 INTTC1 F1H enable INTTC2& INTETC23 INTTC3 F2H enable INTTC4& INTETC45 INTTC5 F3H enable INTTC6& INTETC67 INTTC7 F4H enable INTWD F7H INTWDT enable Interrupt request flag IxxM2 IxxM1 ...
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External interrupt control Symbol Name Address 7 Interrupt 00F6H input IIMC (Prohibit mode RMW) control Interrupt 00FAH input IIMC2 (Prohibit mode RMW) control2 Detect edge Note 1: Disable INT0 to INT3 before changing INT0 to 3 pins mode from ...
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Table 3.4.2 Function Setting of External Interrupt Pin Interrupt Pin Shared Pin INT0 PC3 INT1 PC1 INT2 PC5 INT3 PC6 INT4 PD0 INT5 PD1 Mode IIMC<I0LE> INT0EDGE = 0 Rising edge IIMC<I0LE> INT0EDGE = 1 Falling ...
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SIO receive interrupt control Symbol Name Address SIO F5H Interrupt SIMC (Prohibit mode RMW) control *INTRX1 level enables 0 Detect edge INTRX1 1 “H” level INTRX1 *INTRX0 rising edge enable 0 Detect edge INTRX0 1 “H” Level INTRX0 7 ...
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Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following ...
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Symbol Name Address DMA0 DMA0V start 100H vector DMA1 DMA1V start 101H vector DMA2 DMA2V start 102H vector DMA3 DMA3V start 103H vector DMA4 DMA4V start 104H vector DMA5 DMA5V start 105H vector DMA6 DMA6V start 106H vector DMA7 DMA7V ...
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Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB ...
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Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may ...
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Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 ...
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Table 3.5.2 I/O Port Setting List (1/2) Ports Input Pins Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 4 P40 to P47 Input port* Output port output Port 5 P50 to ...
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Table 3.5.3 I/O Port Setting List (2/2) Ports Input Pins Port A PA0, PA1, Input port PA2, PA7 Port C PC0, PC1, Input port PC3, PC5, Output port PC6 PC0 TA0IN input PC1 TA1OUT output INT1 input PC3 INT0 input ...
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Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, ...
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P1 Bit symbol P17 (0004H) Read/Write After reset 7 P1CR (0006H) Bit symbol P17C P16C Read/Write After reset 0 Function 7 Bit symbol P1FC Read/Write (0007H) After reset Function Note 1: Read-modify-write instruction is prohibited for registers P1FC and ...
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Port 4 (P40 to P47) Port 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O ...
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P4 Bit symbol P47 (0010H) Read/Write After reset 7 Bit symbol P47C P46C P4CR (0012H) Read/Write After reset 0 Function 7 P4FC Bit symbol P47F P46F (0013H) Read/Write After reset 1 Function Note1: Read-modify-write instruction is prohibited for registers ...
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Port 5 (P50 to P57) Port 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O ...
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P5 Bit symbol P57 (0014H) Read/Write After reset 7 Bit symbol P57C P56C P5CR (0016H) Read/Write After reset 0 Function 7 Bit symbol P57F P56F P5FC (0017H) Read/Write After reset 1 Function Note1: Read-modify-write instruction is prohibited for registers ...
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Port 6 (P60 to P67) Port 8-bit general-purpose I/O port*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O ...
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P6 Bit symbol P67 (0018H) Read/Write After reset 7 Bit symbol P67C P6CR (001AH) Read/Write After reset 0 Function 7 Bit symbol P67F P6FC (001BH) Read/Write After reset 1 Function Note1: Read-modify-write instruction is prohibited for registers P6CR and ...
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Port 7 (P70 to P76) Port 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. ...
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Direction control Function control Internal WAIT signal 7 P7 Bit symbol (001CH) Read/Write After reset Data from external port (Note) Note: Output latch register is cleared P7CR Bit symbol P76C (001EH) Read/Write After reset 0: Input Function ...
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Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets output latch of P82 to “0” and set output latches of P80, P81, and P83 to “1”. In addition to functioning as a output port, port ...
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Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or output. In addition to functioning as a general-purpose I/O port, port 9 can also function as a serial ...
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Bit symbol P9 (0024H) Read/Write After reset 7 Bit symbol P9CR P9CR (0026H) (0026H) Read/Write After reset Function 7 Bit symbol P9FC P9FC (0027H) (0027H) Read/Write After reset Function 7 Bit symbol P9ODE (0025H) Read/Write After reset Function Note1: ...
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Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor Bit symbol PA7 (0028H) Read/Write R After reset Data from external port PA read Figure 3.5.16 Port A Port A Register ...
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Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to input port. In addition to functioning as a general-purpose ...
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PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT), PC6 (INT3, TB0OUT0) In addition to function as I/O port, port PC1, PC5, and PC6 can also function as external interrupt input pin INT1 to INT3 and output pin of timer channel TA1OUT, ...
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PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Reset Direction control (on bit basis) PCCR write Function control (on bit basis) PCFC write S Output latch PC read ...
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Bit symbol PC (0030H) Read/Write After reset Data from external Note: Output latch register is set Bit symbol PC6C PCCR PCCR (0032H) (0032H) Read/Write After reset Function 0: Input 1: Output 7 Bit symbol PC6F PCFC ...
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Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port D to input port. In addition to functioning as a general-purpose I/O port, port ...
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PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer channel output pins TB1OUT0 and TB1OUT1. Reset Direction control (on bit basis) PDCR write Function control (on bit ...
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PD Bit symbol (0034H) Read/Write After reset 7 Bit symbol PDCR (0036H) Read/Write After reset Function 7 PDFC Bit symbol (0037H) Read/Write After reset Function Note 1: Read-modify-write instruction is prohibited for the registers PDFC and PDCR. Note 2: ...
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Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting resets the PFCR and PFFC to “0”, and sets all bits to input port. And all ...
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Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD input pin of serial channel. Reset Direction control (on bit basis) PFCR write S Output latch ...
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Port PF2 ( , SCLK0) and port PF5 ( CTS0 In addition to function as I/O port, port PF2 and PF5 can also function as pin of serial channel or SCLK I/O pin. Reset Direction control (on bit basis) ...
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PF Bit symbol PF7 (003CH) Read/Write After reset 7 Bit symbol PF7C PFCR PFCR (003EH) (003EH) Read/Write After reset 0 Function 7 − Bit symbol PFFC PFFC (003FH) (003FH) Read/Write After reset 0 Function Always Always write “0”. write ...
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Port G (PG0 to PG7) Port G is 8-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. PG ...
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Memory Controller 3.6.1 Function TMP92CM22 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area. (2) Connecting memory ...
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Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. • ...
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Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area ...
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Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows Bit symbol M1S23 M1S22 Setting value 0 0 M1S23 to M1S16 bits of the memory ...
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Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. TMP92CM22 ...
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Data Size Start Data Width in (Bit) Address Memory Side (Bit ...
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Wait control The external bus cycle completes a wait of two states at least (100 MHz). Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in the read cycle and the write cycle. ...
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When not inserting a dummy (0 waits) CLKOUT Address CSm CSn RD • When inserting a dummy cycle (0 waits) Dummy CLKOUT Address CSm CSn RD 92CM22-85 TMP92CM22 2007-02-16 ...
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Bus access timing • External read/write bus cycle (0 waits CLKOUT (20 MHz) CS Address output • External read/write bus cycle (1 wait CLKOUT (20 MHz) CS ...
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External read/write bus cycle (0 waits CLKOUT (20 MHz) CS Address Output WAIT Sampling • External read/write bus cycle (n waits CLKOUT (20 MHz) CS ...
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Example of FF0 RES CLKOUT CSn R D WRLL WRLU 1 2 CLKOUT (20 MHz) CSn RD FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT input cycle (5 waits) WAIT FF1 FF2 FF3 ...
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Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This example connects ROM and SRAM in 16-bit width. TMP92CM22 RD WRLL WRLU R/ W CS0 D [15:0] A0 Not connetion A1 ...
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ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CM22 supports ROM ...
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List of Registers The memory control registers and the settings are described as follows. For the addresses of the registers, see list of special function registers in section 5. (1) Control registers The control register is a pair of ...
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B2REC Sets the dummy cycle for data output recovery time Not insert a dummy cycle (Default Insert a dummy cycle B2OM[1: SRAM or ROM (Default) Others = (Reserved) B2BUS[1:0] Sets the data bus width. ...
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Bit symbol BEXWW2 Read/Write After reset 0 BEXWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 101 = 4 states (2 waits) access 111 = 6 states (4 waits) access Others = (Reserved) ...
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Block address area specification register A start address and range in the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address ...
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Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area Bit symbol Read/Write After reset OPGE Enable bit ROM ...
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B0CSL Bit symbol (0140H) Read/Write After reset B0CSH Bit symbol B0E (0141H) Read/Write After reset 0 MAMR0 Bit symbol M0V20 (0142H) Read/Write After reset 1 MSAR0 Bit symbol M0S23 (0143H) Read/Write After reset 1 B1CSL Bit symbol (0144H) Read/Write ...
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Caution If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal possible that an unintended read cycle occurs due to a delay in the read signal. Such ...
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The cautions at the time of the functional change chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control ...
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Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit ...
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Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 92CM22-100 TMP92CM22 2007-02-16 ...
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Figure 3.7.2 TMRA23 Block Diagram 92CM22-101 TMP92CM22 2007-02-16 ...
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Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler’s operation can be controlled using TA01RUN<TA0PRUN> in the timer control register. Setting <TA0PRUN> to “1” starts the count; setting <TA0PRUN> to “0” ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 TA01RUN Bit symbol TA0RDE (1100H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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Bit symbol TA01M1 TA01MOD (1104H) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode Note: When set TA0IN pin, set TA01MOD after set port C. ...
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TA23MOD Bit symbol TA23M1 (110CH) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register TA23M0 PWM21 PWM20 TA3CLK1 R/W ...
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TA1FFCR Bit symbol (1105H) Read/Write After reset Function Read-modify -write instruction is prohibited. Note: The values of bits TA1FFCR are undefined when read. TMRA1 Flip Flop Control Register TA1FFC1 00: Invert TA1FF ...
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TA3FFCR Bit symbol (110DH) Read/Write After reset Function Read-modify -write instruction is prohibited. Note: The values of bits TA3FFCR are undefined when read TMRA3 Flip-Flop Control Register TA3FFC1 00: Invert TA3FF 01: ...
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Timer Register (TA0REG to TA3REG) Symbol Address TA0REG 1102H TA1REG 1103H TA2REG 110AH TA3REG 110BH Note: Read-modify-write instruction is prohibited for above registers Undefined Undefined Undefined Undefined Figure 3.7.9 Register for TMRA 92CM22-110 TMP92CM22 3 2 ...
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Operation in Each Mode 3.7.4 (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. When set function and count data, TMRA0 and TMRA1 should be stopped. 1. Generating interrupts at a fixed interval ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 μs square wave pulse ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator (Match output forTMRA0) TMRA0 up counter 1 (when ...
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The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse ...
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In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be ...
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Example: To generate 1/4 duty 62.5 kHz pulses (at f Calculate the value that should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be 1/62.5 kHz = 16 ...
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PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output ...
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In this mode, the value of the register buffer will be shifted into TA0REG if 2 detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG ...
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Table 3.7.4 Relationship of PWM Cycle and 2 Clock gear System clock − SYSCR1 SYSCR0 <GEAR2:0> <SYSCK> TAxxMOD<TAxCLK1:0> φT1(x2) 000(x1) 1024/fc 001(x2) 2048/fc ×8 0(fc) 010(x4) 4096/fc 011(x8) 8192/fc 100(x16) 16384/fc (5) Mode settings Table 3.7.5 shows the SFR settings ...
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Timer/Event Counters (TMRB) The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which have the following operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable square wave pulse generation output mode (PPG: ...
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Block Diagram Figure 3.8.1 Block Diagram of TMRB0 92CM22-121 TMP92CM22 2007-02-16 ...
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Figure 3.8.2 Block Diagram of TMRB1 92CM22-122 TMP92CM22 2007-02-16 ...
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Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0 divided clock (Divided by 8) from selected clock by the register SYSCR1<GEAR1:0> of clock gear. This prescaler can be started or ...
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Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go ...
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Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L) These 16-bit registers are used to latch the values in the up counters UC10. Data in the capture registers should be read both upper and lower all 16 bits. For example, using ...
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Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match match is detected, ...
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SFRs 7 TB0RUN Bit symbol TB0RDE (1180H) Read/Write R/W After reset 0 Function Double Always buffer write “0”. 0: Disable 1: Enable Note: The values of bits 1, 4, and 5 of TB0RUN are undefined when read. 7 TB1RUN ...
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TB0MOD Bit symbol (1182H) Read/Write R/W After reset 0 Read-modify Function Always -write write “0”. instruction is prohibited TMRB0 Mode Register − TB0CP0I TB0CPM1 Always Software Capture timing write “0”. capture ...
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TB1MOD Bit symbol TB1CT1 (1192H) Read/Write R/W After reset 0 Function TB1FF1 Inversion trigger Read-modify -write 0: Trigger disable instruction is 1: Trigger enable prohibited Invert when UC12 is loaded into TB1CP1H/L TMRB1 Mode Register TB1ET1 ...
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TB0FFCR Bit symbol (1183H) Read/Write W After reset 1 Function Always write “11”. Read-modify -write instruction is prohibited TMRB0 Flip-flop Control Register − TB0C1T1 TB0C0T1 TB0E1T1 R TB0FF0 inversion trigger 0: Trigger ...
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TB1FFCR Bit symbol TB1FF1C1 (1193H) Read/Write W* After reset 1 Function TB1FF1 control Read-modify 00: Invert -write 01: Set instruction is 10: Clear prohibited 11: Don’t care * Always read as “11”. TMRB1 Flip-flop Control Register ...
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TB0RG0L bit Symbol (1188H) Read/Write After reset TB0RG0H bit Symbol (1189H) Read/Write After reset TB0RG1L bit Symbol (118AH) Read/Write After reset TB0RG1H bit Symbol (118BH) Read/Write After reset TB0CP0L bit Symbol (118CH) Read/Write After reset TB0CP0H bit Symbol (118DH) ...
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Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example, the interval time is set the timer register TB0RG1H/L to generate the interrupt INTTB01 ...
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Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the ...
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The following block diagram illustrates this mode. Selector TB0IN0 φT1 φT4 φT16 16-bit comparator TB0RG0H/L Selector TB0RG0-WR Register buffer 10 TB0RUN<TB0RDE> Figure 3.8.11 Block Diagram of 16-Bit PPG Mode The following example shows how to set 16-bit PPG output mode: ...
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Capture function examples Used capture function, they can be applicable in many ways, for example: 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Measurement of difference time 1. One-shot pulse output ...
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Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin. Setting in Main ← TB1MOD ← ...
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Count clock (Prescaler output clock) c TB1IN0 input Load into capture register TB1CP0H/L (External trigger pulse) generate INT4. Match with TB1RG1H/L Inversion enable Timer output TB1OUT0 pin Set it to enable that inversion caused by loading into TB1CP0H/L. Figure 3.8.13 ...
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Pulse width measurement This mode allows measuring the high level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the prescaler output clock input, external pulse is input through the TB1IN0 pin. Then ...
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Measurement of difference time This mode is used to measure the difference in time between the rising edges of external pulses input through TB1IN0 and TB1IN1. Keep the 16-bit timer/event counter (TMRB1) counting (Free running) with the prescaler output ...
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Serial Channels (SIO) The TMP92CM22 includes 2 serial I/O channels. Each channel is called SIO0 and SIO1. For both channels either UART Mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode • ...
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Mode 0 (I/O interface mode) Bit0 1 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 Parity Start Bit0 • Mode 2 (8-bit UART mode) No parity Start Bit0 Parity Start Bit0 • Mode 3 (9-bit ...
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Block Diagram Prescaler φ φT2 φT8 Serial clock generation circuit BR0CR<BR0CK1:0> BR0CR <BR0S3:0> φT0 φT2 φT8 φT32 Baud rate generater f io SCLK0 input (Shared with PF2) I/O interface mode SCLK0 output (Shared with ...
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Prescaler φ φT2 φT8 Serial clock generation circuit BR1CR<BR1CK1:0> BR1CR <BR1S3:0> φT0 φT2 φT8 φT32 Baud rate generater f io SCLK1 input (Shared with PF5) I/O interface mode SCLK1 output (Shared with PF5) Receive control ...
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Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR1<GEAR2:0> is divided by 8 and input to the prescaler as φT0. The prescaler can be run only ...
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Baud rate generator The baud rate generator is a circuit that generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32, is ...
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Integer divider (N divider) For example, when the f C frequency divider N (BR0CR<BR0S3:0> and BR0CR<BR0ADDE> the baud rate in UART mode is as follows: ∗ Clock state Clock gear: 1 /32 Baud ...
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Table 3.9.3 UART Baud Rate Selection (when using baud rate generater and BR0CR<BR0ADDE> [MHz] SYS Frequency Divider 9.8304 2 ↑ 4 ↑ 8 ↑ 10 12.2880 5 ↑ A 14.7456 2 ↑ 3 ↑ 6 ↑ C ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> the basic clock is generated by dividing the output ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When bits ...
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Handshake function Use of CTS0 errors can be avoided. The handshake function is enabled or disabled by the SC0MOD0<CTSE> setting. When the CTS0 transmission, data transmission is halted until the However, the INTTX0 interrupt is generated, and it requests the ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an ...
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Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. 3. Framing error ...
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SFRs 7 SC0MOD0 Bit symbol TB8 (1202H) Read/Write After reset 0 Function Transfer Handshake data bit8 function control 0: CTS 1: CTS Figure 3.9.7 Serial Mode Control Register 0 (for SIO0 and SC0MOD0 CTSE RXE WU ...
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SC1MOD0 Bit symbol TB8 (120AH) Read/Write After reset 0 Function Transfer Handshake data bit8 function control 0: CTS 1: CTS Figure 3.9.8 Serial Mode Control Register (for SIO1 and SC1MOD CTSE RXE WU R ...
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SC0CR Bit symbol RB8 (1201H) Read/Write R After reset Undefined Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. ...
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SC1CR Bit symbol RB8 (1209H) Read/Write R After reset Undefined Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. ...
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BR0CR Bit symbol BR0ADDE (1203H) Read/Write After reset 0 + (16 − K)/16 Function Always write “0”. division 0: Disable 1: Enable + (16 − K)/16 divisions enable 0 Disable 1 Enable 7 BR0ADD Bit symbol (1204H) Read/Write ...
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BR1CR Bit symbol BR1ADDE (120BH) Read/Write After reset 0 + (16 − K)/16 Function Always write “0”. division 0: Disable 1: Enable + (16 − K)/16 divisions enable 0 Disabled 1 Enabled 7 BR1ADD Bit symbol (120CH) Read/Write ...
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TB7 SC0BUF (1200H) 7 RB7 Note: Prohibit read-modify-write for SC0BUF Figure 3.9.13 Serial Transmission/Receiving Buffer Register (for SIO0 and SC0BUF) 7 SC0MOD1 Bit symbol I2S0 (1205H) Read/Write R/W After reset 0 Function IDLE2 Duplex 0: Stop 0: Half 1:Run ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is outputted, INTES0<ITX0C> will be ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit ...
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Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to “0” and set enable the interrupt level ( the transfer interrupts. In the transfer interrupt program, ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel mode register SC0MOD0<SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the ...
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Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is programmed to SC0MOD0<TB8>. In the case ...
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Protocol 1. Select 9-bit UART mode on the master and slave controllers. 2. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for ...
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Example: To link two slave controllers serially with the master controller using the system clock f as the transfer clock. IO TXD RXD TXD Master Slave 1 Select code 00000001 • Master controller setting Main routine ← − − − ...
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Support for IrDA Mode SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Transmission data SIO0 Receive data TMP92CM22 Figure 3.9.24 Block Diagram of IrDA (1) Modulation of transmission data When ...
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Data format Format of transmission/receiving must set to data length 8-bit, without parity bit, 1 bit of stop bit. Any other settings don’t guarantee the normal operation. (4) SFR Figure 3.9.27 shows the control register SIRCR. If change setting ...
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As the same reason, + (16 − K)/16 division function in the baud rate generator of SIO0 cannot be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 division ...
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Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus interface. Serial bus interface (SBI0) include following 2 operation modes. • bus mode (Multi master) 2 • Clocked-synchronous 8-bit SIO mode The serial bus interface is ...
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Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface 0 control register 1 (SBI0CR1) • Serial bus interface 0 control register 2 (SBI0CR2) • Serial bus interface ...
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I C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I 7 SBI0CR1 Bit symbol BC2 (1240H) Read/Write After reset 0 ...
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SBI0CR2 Bit symbol MST (1243H) Read/Write After reset 0 Read- Function Master/ modify-write slave instruction is selection prohibited. Note 1: Reading this register function as SBI0SR register. Note 2: Switch a mode to port mode after confirming that the ...
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SBI0SR Bit symbol MST (1243H) Read/Write After reset 0 Read- Function Master/ modify-write slave instruction is status prohibited. selection monitor Note: Writing in this register functions as SBI0CR2. Serial Bus Interface Status Register TRX BB PIN ...
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SBI0BR0 Bit symbol (1244H) Read/Write W After reset 0 Read- Function Always modify-write write “0”. instruction is prohibited. 7 SBI0BR1 Bit symbol P4EN (1245H) Read/Write W After reset 0 Read- Internal Function modify-write clock instruction is 0: Stop ...
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Control Bus Mode (1) Acknowledge mode specification Set the SBI0CR1<ACK> for operation in the acknowledge mode. The TMP92CM22 generates an additional clock pulse for an acknowledge signal when operating in master mode. In ...
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Clock synchronization In the I C bus mode, in order to wired-AND a bus, a master device which pulls 2 down a clock line to low level, in the first place, invalidate a clock pulse of another master device ...
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Transmitter/receiver selection Set the SBI0CR2<TRX> to “1” for operating the TMP92CM22 as a transmitter. Clear the <TRX> to “0” for operation as a receiver. In slave mode, when transfer data in addressing format, when received slave address is same ...
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Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 (INTSBE0) occurs, the SBI0SR2 <PIN> is cleared to “0”. During the time that the SBI0SR2<PIN> is “0”, the SCL line is pulled down to the ...
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The TMP92CM22 compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to “1”. ...
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Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. When write first “10” next “01” to SBI0CR2<SWRST1:0>, reset signal is inputted to serial bus interface circuit, ...
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Data Transfer Bus Mode (1) Device initialization In first, set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>. Set SBI0BR1<P4EN> to “1” and clear bits and 3 in the SBI0CR1 to “0”. Next, set a slave ...
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SCL line 1 SDA line A6 Start condition <PIN> INTSBE0 interrupt request Figure 3.10.13 Start Condition and Slave Address Generation (3) 1-word data transfer Check the <MST> by the INTSBE0 interrupt process after the 1-word data transfer is completed, and ...
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When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the received data from SBI0DBR to release the SCL line (Data which is read immediately after a slave ...
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If <MST> (Slave mode) In the slave mode the TMP92CM22 operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request generate when the TMP92CM22 receives a ...
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Stop condition generation When SBI0SR<BB> the sequence for generating a stop condition is started by writing “111” to SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST, TRX, PIN, BB> until a ...
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Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when this device is in the master mode. Clear the SBI0CR2<MST, ...
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Clocked-synchronous 8-bit SIO Mode Control The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode. 7 SBI0CR1 Bit symbol SIOS (1240H) Read/Write ...
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SBI0CR2 Bit symbol (1243H) Read/Write After reset Read- Function modify-write instruction is prohibited. Note 1: Set the SBI0CR1<BC2:0> to “000” before switching to a clocked-synchronous 8-bit SIO mode. Note 2: Please always write “00” to SBICR2<1:0>. 7 SBI0SR Bit ...
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Serial Clock 1. Clock source SBI0CR1<SCK2:0> is used to select the following functions: Internal clock In internal clock mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the SCK pin. ...
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Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK ...
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Transfer modes The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive mode. 1. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR. After the transmit data has been ...
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SCK pin (Output pin * INTSBE0 interrupt request SBI0DBR a b Writing transmission data <SIOS> <SIOF> <SEF> SCK pin (Input) SO pin INTSBE0 ...
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SCK pin <SIOF> Bit6 SO pin Figure 3.10.26 Transmission Data Hold Time at End Transmit 2. 8-bit receive mode Set the control register to receive mode and set the SBI0CR1<SIOS> to “1” for switching to receive mode. Data is received ...
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SCK pin (Output pin INTSEB0 interrupt request SBI0DBR Figure 3.10.27 Receiver Mode (Example: Internal clock) 3. 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBI0DBR. After ...
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SCK pin (Output pin * pin INTSBE0 Interrupt interrupt a SBI0DBR Write transmission data (a) Figure 3.10.28 Transmission/Receiving Mode (when an external clock ...