TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 199

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
SI pin
INTSEB0
interrupt request
SBI0DBR
Note: When the transfer mode is changed, the contents of the SBI0DBR will be lost. If the mode
must be changed, conclude data transmitting/receiving by clearing the <SIOS> to “0”, read
the last data, and then change the transfer mode.
3.
8-bit transmit/receive mode
After the data is written, set the SBI0CR<SIOS> to “1” to
transmitting/receiving. When data is transmitted, the data is output from the SO
pin, starting from the least significant bit (LSB) and synchronized with the
leading edge of the serial clock signal. When data is received, the data is input via
the SI pin on the trailing edge of the serial clock signal. 8-bit data is transferred
from the shift register to the SBI0DBR and the INTSBE0 interrupt request is
generated. The interrupt service program reads the received data from the data
buffer register and writes the data which is to be transmitted. The SBI0DBR is
used for both transmitting and receiving. Transmitted data should always be
written after received data is read.
until the received data is read and the new data is written.
the external clock, the received data is read and transmitted data is written before
a new shift operation is executed. The maximum transfer speed when the external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time at which received data is read and transmitted
data is written.
SO pin holds final bit of the last data until falling edge of the SCK.
INTSBE0 interrupt service program or when the SBI0CR1<SIOINH> is set to “1”.
When the <SIOS> is cleared to “0”, received data is transferred to the SBI0DBR in
complete blocks. The transmit/receive mode ends when the transfer is completed.
In order to confirm whether data is being transmitted/received properly by the
program, set the SBI0SR to be sensed. The <SIOF> is cleared to “0” when
transmitting/receiving is completed. When the <SIOINH> is set to “1”, data
transmitting/receiving stops. The <SIOF> is then cleared to “0”.
Figure 3.10.27 Receiver Mode (Example: Internal clock)
Set a control register to a transmit/receive mode and write data to the SBI0DBR.
When the internal clock is used, the automatic wait function will be in effect
When the external clock is used, since the shift operation is synchronized with
When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the
Transmitting/receiving data ends when the <SIOS> is cleared to “0” by the
a 0
a 1
a 2
a 3
92CM22-197
a 4
a 5
Read receive data
a 6
a 7
a
b 0
b 1
b 2
Clear <SIOS>
b 3
b 4
b 5
Read receive data
b 6
b 7
b
TMP92CM22
2007-02-16
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