TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 75

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.5.11
Port F (PF0 to PF7)
output. Resetting resets the PFCR and PFFC to “0”, and sets all bits to input port. And all
bits of output latch register to “1”.
function of serial channel 0 and 1.
(1) Port PF0 and PF3 (TXD0/TXD1)
pin of serial channel.
PFFC<PF0F, PF3F> and PFCR<PF0C, PF3C> register.
Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or
In addition to functioning as a general-purpose I/O port, port F can also function as I/O
These settings operate by writing “1” to the corresponding bit of PFFC.
Resetting resets the PDCR and PDFC to “0”, and sets all bits to input port.
Thus, output buffer feature a programmable open-drain function, and setting enable by
In addition to function as I/O port, port PF0 and PF3 can also function as TXD output
Direction control
Function control
(on bit basis)
(on bit basis)
Output latch
PFCR write
PFFC write
PF write
Reset
S
PF read
TXD0, TXD1
Figure 3.5.25 Port F (PF0 and PF3)
92CM22-73
A
B
Selector
S
Selector
S
B
A
<PF0F = 1, PF0C = 0
PF3F = 1, PF3C = 0>
Open-drain enable
PF0 (TXD0)
PF3 (TXD1)
TMP92CM22
2007-02-16