TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 5

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

PC6 (TB00UT0/INT3)
PC1 (TA1OUT/INT1)
PC5 (TA3OUT/INT2)
PF2 (SCLK0/
PF5 (SCLK1/
PD0 (TB1IN0/INT4)
PD1 (TB1IN1/INT5)
PD2 (TB1OUT0)
PD3 (TB1OUT1)
PG3 (
P91 (SO/SDA)
(AN0 to AN7)
P92 (SI/SCL)
PC0 (TA0IN)
PF1 (RXD0)
PF4 (RXD1)
PG0 to PG7
PF0 (TXD0)
PF3 (TXD1)
PF6 to PF7
P90 (SCK)
ADTRG
VREFH
VREFL
CTS0
AVCC
CTS1
AVSS
)
)
)
16-bit timer
16-bit timer
10-bit 8-ch
(Timer A0)
(Timer A1)
(Timer A2)
(Timer A3)
(Timer B0)
(Timer B1)
8-bit timer
8-bit timer
8-bit timer
8-bit timer
converter
Serial I/O
Serial I/O
bus I/F
Port F
Serial
SIO0
SIO1
SBI0
AD
Figure 1.1 TMP92CM22 Block Diagram
XWA
XBC
XDE
XSP
XHL
XIX
XIY
XIZ
92CM22-3
Watchdog timer
32-Kbyte RAM
SR
32 bits
900/H1 CPU
P C
W
B
D
H
SP
IX
IY
IZ
A
C
E
F
L
Clock gear
controller
controller
Data bus
Interrupt
H-OSC
Port A
Port 1
Port 4
Port 5
Port 6
Port 7
Mode
Port 8
PLL
TMP92CM22
2007-02-16
DVCC [3]
X1
DVSS [4]
X2
P80 (
AM0
AM1
PC3(INT0)
D0 to D7
P10 to P17
(D8 to D15)
P40 to P47
(A0 to A7)
P50 to P57
(A8 to A15)
P60 to P67
(A16 to A23)
P70 (
P71 (
P72 (
P73
P74 (CLKOUT)
P75 (R/
P76 (
P81 (
P82 (
P83 (
PA0 to PA2
PA7
RESET
NMI
CS0
RD
CS1
CS2
CS3
WRLL
WRLU
WAIT
W
)
)
)
)
)
)
)
)
)