TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 186

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.10.6
Data Transfer in I
(1) Device initialization
(2) Start condition and slave address generation
to “1” and clear bits 7 to 5 and 3 in the SBI0CR1 to “0”.
format) to the I2C0AR.
“00” to <SWRST1:0>. Set initialization status to slave receiver mode by this setting.
1.
2.
In first, set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>. Set SBI0BR1<P4EN>
Next, set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing
And, write “000” to SBI0CR2<MST, TRX, BB>, “1” to <PIN>, “10” to <SBIM1:0> and
Master mode
follows.
Set the SBI0CR1<ACK> to “1” (Acknowledge mode) and specify a slave address
and a direction bit to be transmitted to the SBI0DBR.
SBI0CR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBI0DBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
<PIN> is cleared to “0”. In the master mode, the SCL pin is pulled down to the low
level while <PIN> is “0”. When an interrupt request is generated, the <TRX> is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.
Slave mode
are output from the SCL pin, the slave address and the direction bit that are
output from the master device are received.
I2C0AR is received, the SDA line is pulled down to the low level at the 9th clock,
and the acknowledge signal is output.
The <PIN> is cleared to “0”. In slave mode the SCL line is pulled down to the low
level while the <PIN> = “0”.
In the master mode, the start condition and the slave address are generated as
In first, check a bus free status (when SBI0SR<BB> = “0”).
When SBI0SR<BB> = “0”, the start condition are generated by writing “1111” to
An INTSBE interrupt request generate at the falling edge of the 9th clock. The
In the slave mode, the start condition and the slave address are received.
After the start condition is received from the master device, while eight clocks
When a GENERAL CALL or the same address as the slave address set in
An INTSBE interrupt request is generated on the falling edge of the 9th clock.
2
C Bus Mode
92CM22-184
TMP92CM22
2007-02-16