TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 182

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SCL line
SDA line
Start condition
(6) Transmitter/receiver selection
(7) Start/stop condition generation
the <TRX> to “0” for operation as a receiver. In slave mode, when transfer data in
addressing format, when received slave address is same value with setting value to
I2C0AR, or GENERAL CALL is received (All 8-bit data are “0” after a start condition),
the <TRX> is set to “1” by the hardware if the direction bit (R/
device is “1”, and <TRX> is cleared to “0” by the hardware if the bit is “0”.
the <TRX> is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is
set to “1” by the hardware if it is “0”. When an acknowledge signal is not returned, the
current condition is maintained.
detected or arbitration is lost.
SBI0SR<BB> is “0”, slave address and direction bit which are set to SBI0DBR and
start condition are output on a bus. And it is necessary to set transmitted data to the
data buffer register (SBI0DBR) and set “1” to <ACK> beforehand.
SBI0SR<BB> is “1”, start a sequence of stop condition output. Do not modify the
contents of <MST, TRX, BB, and PIN> until a stop condition is generated on a bus.
SBI0SR<BB> will be set to 1 (Bus busy status) if a start condition has been detected on the
bus, and will be cleared to 0 if a stop condition has been detected (Bus free status).
Set the SBI0CR2<TRX> to “1” for operating the TMP92CM22 as a transmitter. Clear
In the master mode, after an acknowledge signal is returned from the slave device,
The <TRX> is cleared to “0” by the hardware after a stop condition on the bus is
When programmed “1111” to SBI0CR2 <MST, TRX, BB, PIN> in during
When programmed “0” to SBI0CR2<BB> and “111” to <MST, TRX, PIN> in during
The state of the bus can be ascertained by reading the contents of SBI0SR<BB>.
Figure 3.10.9 Generation of Start Condition and Slave Address
A6
1
SCL line
SDA line
Figure 3.10.10 Generation of Stop Condition
A5
2
A4
3
Slave address and direction bit
92CM22-180
A3
4
Stop condition
A2
5
A1
6
A0
7
W
R/
) sent from the master
8
W
Acknowledge
signal
TMP92CM22
9
2007-02-16