FAN3229C Fairchild Semiconductor, FAN3229C Datasheet - Page 19

• Manufacturer Part Number: FAN3229C
• Description: The FAN3226-29 family of dual 2A gate drivers is designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals
• Manufacturer: Fairchild Semiconductor

© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.8
Truth Table of Logic Operation
The FAN3228/FAN3229 truth table indicates the
operational states using the dual-input configuration. In
a non-inverting driver configuration, the IN- pin should
be a logic low signal. If the IN- pin is connected to logic
high, a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
In the non-inverting driver configuration in Figure 51, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
high to disable the driver and the output remains low,
regardless of the state of the IN+ pin.
In the inverting driver application in Figure 52, the IN+
pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
PWM
IN+
Figure 51. Dual-Input Driver Enabled,
Figure 52. Dual-Input Driver Enabled,
0
0
1
1
Non-Inverting Configuration
Inverting Configuration
IN+
IN-
IN-
0
1
0
1
FAN3228/9
VDD
GND
OUT
0
0
1
0
OUT
19
Operational Waveforms
At power-up, the driver output remains low until the V
voltage reaches the turn-on threshold. The magnitude of
the OUT pulses rises with V
reached. The non-inverting operation illustrated in
Figure 53 shows that the output remains low until the
UVLO threshold is reached, the output is in-phase with
the input.
For the inverting configuration of Figure 52, startup
waveforms are shown in Figure 54. With IN+ tied to V
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power-up, the
inverted output remains low until the V
reaches the turn-on threshold, then it follows the input
with inverted phase.
Figure 53. Non-Inverting Startup Waveforms
Figure 54. Inverting Startup Waveforms
DD
until steady-state V
www.fairchildsemi.com
DD
voltage
DD
DD
DD
is