FAN3229C Fairchild Semiconductor, FAN3229C Datasheet - Page 2

• Manufacturer Part Number: FAN3229C
• Description: The FAN3226-29 family of dual 2A gate drivers is designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals
• Manufacturer: Fairchild Semiconductor

© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.8
Ordering Information
Part Number
FAN3226CMPX
FAN3226CMX
FAN3226TMPX
FAN3226TMX
FAN3227CMPX
FAN3227CMX
FAN3227TMPX
FAN3227TMX
FAN3228CMPX
FAN3228CMX
FAN3228TMPX
FAN3228TMX
FAN3229CMPX
FAN3229CMX
FAN3229TMPX
FAN3229TMX
Package Outlines
Thermal Characteristics
8-Lead 3x3mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1.
2.
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (
thermal pad) that are typically soldered to a PCB.
Theta_JT (
held at a uniform temperature by a top-side heatsink.
Theta_JA (Θ
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (
application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (
the center of the top of the package for the thermal environment defined in Note 4.
Figure 2. 3x3mm MLP-8 (Top View)


JB
JT


): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
JL
JT
JA
Dual Inverting Channels +
Dual Enable
Dual Non-Inverting Channels
+ Dual Enable
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 1
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 2
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
Package
Logic
(1)
Threshold
Input
CMOS
CMOS
CMOS
CMOS
TTL
TTL
TTL
TTL
2
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8

1.6
40
JL
(2)
Package
Figure 3. SOIC-8 (Top View)

68
31
JT
(3)

JA
43
89
Packing Method
(4)
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel

3.5
43
JB
(5)

0.8
3.0
JT
www.fairchildsemi.com
(6)
Quantity
per Reel
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
Units
°C/W
°C/W