CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 16

• Manufacturer Part Number: CYWUSB6935
• Description: Lr 2.4-ghz Dsss Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16008 Rev. *D
Bit
7
6:0
Bit
7
6:0
Bit
7:1
0
Bit
7:1
0
Reserved
Reserved
Name
Reserved
Wakeup Enable Wakeup interrupt enable.
Name
Reserved
Threshold Low
Name
Reserved
Wakeup Status
Name
Reserved
Threshold High
7
7
7
7
Addr: 0x1A
Addr: 0x1C
Addr: 0x1D
Addr: 0x19
Description
These bits are reserved and should be written with zeroes.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
Description
These bits are reserved. This register is read-only.
Wakeup status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg
0x1D). This register is read-only.
Description
This bit is reserved and should be written with zero.
The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a
single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero
correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low value
to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This
value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold
values used determine the sensitivity of the receiver to interference and the dependability of the received data. By
allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness
to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data
integrity but increased robustness to interference and increased range.
6
6
6
6
Description
This bit is reserved and should be written with zero.
The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate a
single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code would
result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By
setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying
the value of the received data bit. This value along with the Threshold Low value determine the correlator count values
for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference and the
dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received
data increases while the robustness to interference decreases. On the other hand increasing the maximum number
of missed chips means reduced data integrity but increased robustness to interference and increased range.
5
5
5
5
Figure 7-18. Threshold High
Figure 7-17. Threshold Low
Figure 7-19. Wake Enable
Figure 7-20. Wake Status
Reserved
Reserved
REG_THRESHOLD_H
REG_THRESHOLD_L
REG_WAKE_STAT
REG_WAKE_EN
4
4
4
4
Threshold High
Threshold Low
3
3
3
3
2
2
2
2
1
1
1
1
CYWUSB6935
Default: 0x01
Default: 0x00
Default: 0x08
Default: 0x38
Wakeup Status
Page 16 of 32
Wakeup En-
able
0
0
0
0
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