CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 2

• Manufacturer Part Number: CYWUSB6935
• Description: Lr 2.4-ghz Dsss Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

3.1
The CYWUSB6935 is supported by both the CY3632
WirelessUSB Development Kit and the CY3635 WirelessUSB
N:1 Development Kit. The CY3635 development kit provides
all of the materials and documents needed to cut the cord on
multipoint to point and point-to-point low bandwidth, high node
density applications including four small form-factor sensor
boards and a hub board that connects to WirelessUSB LR RF
module boards, a software application that graphically demon-
strates the multipoint to point protocol, comprehensive
WirelessUSB protocol code examples and all of the
associated schematics, gerber files and bill of materials. The
WirelessUSB N:1 Development Kit is also supported by the
WirelessUSB Listener Tool.
4.0
The CYWUSB6935 provides a complete SPI-to-antenna radio
modem. The CYWUSB6935 is designed to implement
wireless devices operating in the worldwide 2.4-GHz Indus-
trial,
(2.400 GHz–2.4835 GHz). It is intended for systems compliant
with world-wide regulations covered by ETSI EN 301 489-1
V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries);
FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB
STD-T66 (Japan).
The CYWUSB6935 contains a 2.4-GHz radio transceiver, a
GFSK modem, and a dual DSSS reconfigurable baseband.
The radio and baseband are both code- and frequency-agile.
Forty-nine spreading codes selected for optimal performance
(Gold codes) are supported across 78 1-MHz channels
yielding a theoretical spectral capacity of 3822 channels. The
CYWUSB6935 supports a range of up to 50 meters or more.
4.1
The receiver and transmitter are a single-conversion,
low-Intermediate Frequency (low-IF) architecture with fully
integrated IF channel matched filters to achieve high perfor-
mance in the presence of interference. An integrated Power
Amplifier (PA) provides an output power control range of 30 dB
in seven steps.
Table 4-1. Internal PA Output Power Step Table
Both the receiver and transmitter integrated Voltage
Controlled Oscillator (VCO) and synthesizer have the agility to
cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The synthesizer provides the frequency-hopping local
Document #: 38-16008 Rev. *D
Scientific,
Applications Support
2.4-GHz Radio
PA Setting
Functional Overview
7
6
5
4
3
2
1
0
and
Medical
Typical Output Power
(ISM)
(dBm)
–16.4
–20.8
–24.8
–29.0
frequency
–2.4
–5.6
–9.7
0
band
oscillator for the transmitter and receiver. The VCO loop filter
is also integrated on-chip.
4.2
The transmitter uses a DSP-based vector modulator to
convert the 1-MHz chips to an accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM)
detector with automatic data slicer to demodulate the GFSK
signal.
4.3
Data is converted to DSSS chips by a digital spreader.
De-spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has three operating modes: 64-chips/bit
Single Channel, 32-chips/bit Single Channel, and 32-chips/bit
Single Channel Dual Data Rate (DDR).
4.3.1
The baseband supports a single data stream operating at
15.625 kbits/sec. The advantage of selecting this mode is its
ability to tolerate a noisy environment. This is because the
15.625 kbits/sec data stream utilizes the longest PN Code
resulting in the highest probability for recovering packets over
the air. This mode can also be selected for systems requiring
data transmissions over longer ranges.
4.3.2
The baseband supports a single data stream operating at
31.25 kbits/sec.
4.3.3
The baseband spreads bits in pairs and supports a single data
stream operating at 62.5 kbits/sec.
4.4
CYWUSB6935
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the
SERDES and receive bytes are read from the SERDES via the
SPI interface. The SERDES provides double buffering of
transmit and receive data. While one byte is being transmitted
by the radio the next byte can be written to the SERDES data
register insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the
next byte is received, at which time the old contents of the
SERDES data register will be overwritten.
4.5
CYWUSB6935 has a fully synchronous SPI slave interface for
connectivity to the application MCU. Configuration and
byte-oriented data transfer can be performed over this
interface. An interrupt is provided to trigger real time events.
GFSK Modem
Dual DSSS Baseband
64 Chips/Bit Single Channel
32 Chips/Bit Single Channel
32 Chips/Bit Single Channel Dual Data Rate (DDR)
Serializer/Deserializer (SERDES)
Application Interfaces
provides
a
data
CYWUSB6935
Serializer/Deserializer
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