MT28F800B3 Micron Technology, MT28F800B3 Datasheet - Page 12

• Manufacturer Part Number: MT28F800B3
• Description: (MT28F008B3 / MT28F800B3) FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
COMMAND EXECUTION
ent operational modes. Each mode allows specific opera-
tions to be performed. Several modes require a sequence
of commands to be written before they are reached. The
following section describes the properties of each mode,
and Table 3 lists all command sequences required to
perform the desired operation.
READ ARRAY
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFh) must be given to return
to the array read mode. Unlike the WRITE SETUP com-
mand (40h), READ ARRAY does not need to be given
before each individual READ access.
IDENTIFY DEVICE
enter the identify device mode. While the device is in this
mode, any READ produces the device identification when
A0 is HIGH and the manufacturer compatibility identifi-
cation when A0 is LOW. The device remains in this mode
until another command is given.
NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
4
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
U
Commands are issued to bring the device into differ-
The array read mode is the initial state of the device
IDENTIFY DEVICE (90h) may be written to the CEL to
.com
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. BA = Block Address (A12–A19).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
CYCLES
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
BUS
1
3
2
1
2
2
2
2
Command Sequences
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
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SMART 3 BOOT BLOCK FLASH MEMORY
Table 3
CYCLE
12
FIRST
X
X
X
X
X
X
X
X
WRITE SEQUENCE
the array. WRITE SETUP (40h or 10h) is given in the first
cycle. The next cycle is the WRITE, during which the write
address and data are issued and V
Writing to the boot block also requires that the RP# pin be
brought to V
same time V
write the word or byte. V
WRITE is completed (SR7 = 1).
(SR7) is at 0, and the device does not respond to any
commands. Any READ operation produces the status
register contents on DQ0–DQ7. When the ISM status bit
(SR7) is set to a logic 1, the WRITE has been completed,
and the device goes into the status register read mode
until another command is given.
aborted except by a RESET or by powering down the part.
Doing either during a WRITE corrupts the data being
written. If only the WRITE SETUP command has been
given, the WRITE may be nullified by performing a null
WRITE. To execute a null WRITE, FFh must be written
Two consecutive cycles are needed to input data to
While the ISM executes the WRITE, the ISM status bit
After the ISM has initiated the WRITE, it cannot be
90h
70h
50h
20h
B0h
10h
FFh
40h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PP
HH
is brought to V
or the WP# pin be brought HIGH at the
WRITE
WRITE
WRITE
WRITE
READ
READ
PP
SECOND
CYCLE
must be held at V
PPH
WA
WA
BA
IA
X
X
. The ISM now begins to
PP
is brought to V
D0h
SRD
D0h
WD
WD
ID
©2001, Micron Technology, Inc.
PPH
NOTES
8Mb
until the
2, 3
5, 6
6, 7
6, 7
1
4
PPH
.