MT28F800B3 Micron Technology, MT28F800B3 Datasheet - Page 13

• Manufacturer Part Number: MT28F800B3
• Description: (MT28F008B3 / MT28F800B3) FLASH MEMORY
• Manufacturer: Micron Technology

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when BYTE# is LOW, or FFFFh must be written when
BYTE# is HIGH. When the ISM status bit (SR7) has been
set, the device is in the status register read mode until
another command is issued.
ERASE SEQUENCE
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To pro-
vide added security against accidental block erasure,
two consecutive command cycles are required to initiate
an ERASE of a block. In the first cycle, addresses are
“Don’t Care,” and ERASE SETUP (20h) is given. In the
second cycle, V
within the block to be erased must be issued, and ERASE
CONFIRM (D0h) must be given. If a command other than
ERASE CONFIRM is given, the write and erase status bits
(SR4 and SR5) are set, and the device is in the status
register read mode.
starts the ERASE of the addressed block. Any READ
operation outputs the status register contents on DQ0–
DQ7. V
pleted (SR7 = 1). When the ERASE is completed, the
device is in the status register read mode until another
command is issued. Erasing the boot block also requires
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
4
SR5
U
Executing an ERASE sequence sets all bits within a
After the ERASE CONFIRM (D0h) is issued, the ISM
0
0
0
0
1
1
1
1
.com
STATUS BITS
PP
must be held at V
SR4
0
0
1
1
0
0
1
1
PP
must be brought to V
SR3
0
1
0
1
0
1
0
1
PPH
ERROR DESCRIPTION
No errors
V
WRITE error
WRITE error, V
ERASE error
ERASE error, V
Command sequencing error or WRITE/ERASE error
Command sequencing error, V
Status Register Error Code Description
PP
until the ERASE is com-
voltage error
PPH
, an address
PP
PP
voltage not valid at time of ERASE CONFIRM
voltage not valid at time of WRITE
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SMART 3 BOOT BLOCK FLASH MEMORY
Table 4
13
PP
that either the RP# pin be set to V
held HIGH at the same time V
ERASE SUSPENSION
ERASE is in progress is ERASE SUSPEND. This com-
mand enables other commands to be executed while
pausing the ERASE in progress. When the device has
reached the erase suspend mode, the erase suspend
status bit (SR6) and ISM status bit (SR7) are set. The
device may now be given a READ ARRAY, ERASE RE-
SUME or READ STATUS REGISTER command. After
READ ARRAY has been issued, any location not within
the block being erased may be read. If ERASE RESUME
is issued before SR6 has been set, the device immedi-
ately proceeds with the ERASE in progress.
ERROR HANDLING
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS REG-
ISTER (50h) must be given. If the V
further WRITE or ERASE operations cannot resume until
the status register is cleared. Table 4 lists the combina-
tion of errors.
voltage error, with WRITE and ERASE errors
The only command that may be issued while an
After the ISM status bit (SR7) has been set, the V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
PP
is set to V
PP
HH
status bit (SR3) is set,
or the WP# pin be
©2001, Micron Technology, Inc.
PPH
.
8Mb
PP