MT28F800B3 Micron Technology, MT28F800B3 Datasheet - Page 8

• Manufacturer Part Number: MT28F800B3
• Description: (MT28F008B3 / MT28F800B3) FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
DEEP POWER-DOWN MODE
MT28F800B3 and MT28F008B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
draw is a maximum of 8µA at 3.3V V
power-down also clears the status register and sets the
ISM to the read array mode.
MEMORY ARCHITECTURE
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func-
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
4
U
To allow for maximum power conservation, the
The MT28F800B3 and MT28F008B3 memory array
.com
WORD ADDRESS
MT28F008B3/800B3xx-xxB
70000h
60000h
50000h
40000h
30000h
20000h
10000h
04000h
03000h
02000h
00000h
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
03FFFh
02FFFh
01FFFh
Bottom Boot
BYTE ADDRESS
SS
A0000h
E0000h
C0000h
80000h
60000h
40000h
20000h
08000h
06000h
04000h
00000h
DFFFFh
BFFFFh
9FFFFh
7FFFFh
5FFFFh
3FFFFh
1FFFFh
07FFFh
05FFFh
03FFFh
±0.2V. In this mode, the current
FFFFFh
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
CC
. Entering deep
Memory Address Maps
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SMART 3 BOOT BLOCK FLASH MEMORY
Figure 1
8
tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.
or WRITE with a hardware protection circuit which re-
quires that a super-voltage be applied to RP# or that the
WP# pin be driven HIGH before erasure is commenced.
The boot block is intended for the core firmware required
for basic system functionality. The remaining ten blocks
do not require that either of these two conditions be met
before WRITE or ERASE operations.
BOOT BLOCK
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (V
of 12V or when the WP# pin is HIGH. During a WRITE or
ERASE of the boot block, the RP# pin must be held at V
or the WP# pin held HIGH until the WRITE or ERASE is
completed. (The WP# pin does not apply to the SOP
package.) The V
the boot block is written to or erased.
The boot block is protected from unintentional ERASE
The hardware-protected boot block provides extra
WORD ADDRESS
MT28F008B3/800B3xx-xxT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7D000h
7E000h
7DFFFh
7C000h
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
7CFFFh
7BFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
PP
pin must be at V
Top Boot
BYTE ADDRESS
FA000h
A0000h
FC000h
E0000h
C0000h
80000h
60000h
40000h
20000h
00000h
F8000h
DFFFFh
FBFFFh
F9FFFh
F7FFFh
BFFFFh
9FFFFh
7FFFFh
5FFFFh
3FFFFh
1FFFFh
FFFFFh
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
PPH
(3.3V or 5V) when
©2001, Micron Technology, Inc.
8Mb
HH
HH
)