HT45R22E Holtek Semiconductor, HT45R22E Datasheet - Page 17

• Manufacturer Part Number: HT45R22E
• Description: Remote Type 8-bit OTP MCU
• Manufacturer: Holtek Semiconductor

System Control Registers - CTRL0, CTRL1
These registers are used to provide control over various internal functions. Some of these include the PFD control, I/O
remapping function, certain system clock options, the LXT Oscillator low power control, external Interrupt edge trigger
type, Watchdog Timer enable function, Time Base function division ratio, and the LXT oscillator enable control.
Rev. 1.00
CTRL0 Register
CTRL1 Register
Bit 7
Bit 6
Bit 5~4
Bit 3~2:
Bit 1
Bit 0
Bit 7, 6
Bit 5, 4
Bit 3~0
Note:
Name
Name
POR
POR
R/W
R/W
Bit
Bit
INTEG1
PCFG
PCFG: I/O configuration
PFDCS: PFD clock source
unimplemented, read as 0
PFDEN[1:0]: PFD/PFDB enable/ disable
LXTLP: LXT oscillator low power control function
CLKMOD: System clock mode selection
This clock mode selection is only valid if the oscillator configuration option has selected the
HIRC+LXT.
INTEG1, INTEG0: External interrupt edge type
TBSEL1, TBSEL0: Time base period selection
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
Other values: WDT enabled - Recommended value is 0101
If the watchdog timer enable is configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0 1010.
R/W
R/W
0: INTB/TC0/PFD pin-shared with PA3/PA2/PA0
1: INTB/TC0/PFD pin-shared with PC5/PC4/PC3
0: Timer 0
1: Timer 1
00: Both disable
01: unimplemented, read as 0
10: PFD enable
11: PFD and PFDB enable
0: LXT oscillator quick start-up mode
1: LXT oscillator Low Power Mode
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
00: 2
01: 2
10: 2
11: 2
1010: WDT disabled
7
0
7
1
13
10
11
12
(1/f
(1/f
(1/f
(1/f
INTEG0
PFDCS
R/W
R/W
TP
TP
TP
TP
6
0
6
0
)
)
)
)
TBSEL1
R/W
5
0
5
0
TBSEL0
17
R/W
4
0
4
0
WDTEN3
PFDEN1
R/W
R/W
3
0
3
1
WDTEN2
PFDEN0
R/W
R/W
2
0
2
0
WDTEN1
LXTLP
R/W
R/W
1
0
1
1
HT45R22E
March 17, 2010
CLKMOD
WDTEN0
www.DataSheet4U.com
R/W
R/W
0
0
0
0