HT45R22E Holtek Semiconductor, HT45R22E Datasheet - Page 37

• Manufacturer Part Number: HT45R22E
• Description: Remote Type 8-bit OTP MCU
• Manufacturer: Holtek Semiconductor

Timer Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal inter-
rupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Regis-
ter must be set to the correct value as shown.
In this mode the internal clock is used as the timer clock.
The timer input clock source is either f
LXT oscillator. However, this timer clock source is fur-
ther divided by a prescaler, the value of which is deter-
mined by the bits TnPSC2~TnPSC0 in the Timer
Control Register. The timer-on bit, TnON must be set
high to enable the timer to run. Each time an internal
clock high to low transition occurs, the timer increments
by one; when the timer is full and overflows, an interrupt
signal is generated and the timer will reload the value al-
ready loaded into the preload register and continue
counting. A timer overflow condition and corresponding
internal interrupt is one of the wake-up sources, how-
Rev. 1.00
Control Register Operating Mode
Select Bits for the Timer Mode
TMR1C Register
Bit 7,6
Bit 5
Bit 4
Bit 3
Bit 2~0
Name
POR
R/W
Bit
T1M1
T1M1, T1M0: Timer 1 operation mode selection
T1S: timer clock source
T1ON: Timer/event counter counting enable
T1EG:
Event counter active edge selection
Pulse width capture active edge selection
unimplemented, read as 0
R/W
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
0: f
1: LXT oscillator
0: disable
1: enable
0: count on raising edge
1: count on falling edge
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
7
0
SYS
/4
T1M0
R/W
6
0
SYS
, f
SYS
Bit7 Bit6
T1S
R/W
Timer Mode Timing Chart
1
5
0
/4 or the
0
T1ON
37
R/W
4
0
ever, the internal interrupts can be disabled by ensuring
that the ETnI bits of the INTCn register are reset to zero.
Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer TCn pin, can be
recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
In this mode, the external timer TCn pin is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnEG, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the TnEG is high, the counter
Control Register Operating Mode
Select Bits for the Event Counter Mode
T1EG
R/W
3
1
2
1
HT45R22E
March 17, 2010
Bit7 Bit6
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0
0
1