HT45R22E Holtek Semiconductor, HT45R22E Datasheet - Page 51

• Manufacturer Part Number: HT45R22E
• Description: Remote Type 8-bit OTP MCU
• Manufacturer: Holtek Semiconductor

Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETnI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, TnF, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a
subroutine call to the relevant timer interrupt vector, will
take place. When the interrupt is serviced, the timer in-
terrupt request flag, TnF, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
Time Base Interrupt
For a time base interrupt to occur the global interrupt en-
able bit EMI and the corresponding interrupt enable bit
ETBI, must first be set. An actual Time Base interrupt
will take place when the time base request flag TBF is
set, a situation that will occur when the Time Base over-
flows. When the interrupt is enabled, the stack is not full
and a time base overflow occurs a subroutine call to
time base vector will take place. When the interrupt is
serviced, the time base interrupt flag, TBF will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Rev. 1.00
MFIC Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
POR
R/W
Bit
unimplemented, read as 0
A1F: OPA1 interrupt request flag
A0F: OPA0 interrupt request flag
CF: Comparator interrupt request flag
unimplemented, read as 0
EA1I: OPA1 interrupt enable
EA0I: OPA0 interrupt enable
ECI: Comparator interrupt enable
0: inactive
1: active
0: inactive
1: active
0: inactive
1: active
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
7
R/W
A1F
6
0
R/W
A0F
5
0
51
R/W
CF
4
0
Multi-function Interrupt
For a Multi-function interrupt to occur, the global inter-
rupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, EMFI, must first be
set. An actual Multi-function interrupt will take place
when the Multi-function interrupt request flag, MFF, is
set, a situation that will occur when OPA0 or OPA1 out-
put has a falling edge, or a Comparator output transition
occurs. When the interrupt is enabled, the stack is not
full and a Multi-function interrupt request occurs, a sub-
routine call to the Multi-function interrupt vector at loca-
tion 18H, will take place. When the interrupt is serviced,
the Multi-function interrupt request flag, MFF, will be au-
tomatically reset and the EMI bit will be automatically
cleared to disable other interrupts. After the
Multi-function took place, the programmer can check
what the interrupt source was by interrogating the re-
quest flags, A0F, A1F or CF within the MFIC register.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
3
EA1I
R/W
2
0
EA0I
R/W
1
0
HT45R22E
March 17, 2010
www.DataSheet4U.com
R/W
ECI
0
0