HT45R22E Holtek Semiconductor, HT45R22E Datasheet - Page 49

• Manufacturer Part Number: HT45R22E
• Description: Remote Type 8-bit OTP MCU
• Manufacturer: Holtek Semiconductor

Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF, is
set, a situation that will occur when an edge transition
Rev. 1.00
Interrupt Source
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Time Base Overflow
Multi-function Interrupt
(Comparator, OPA0, OPA1)
Priority Vector
1
2
3
4
5
0CH
04H
08H
14H
18H
Interrupt Scheme
49
appears on the external INT line. The type of transition
that will trigger an external interrupt, whether high to
low, low to high or both is determined by the INTEG0
and INTEG1 bits, which are bits 6 and 7 respectively, in
the CTRL1 control register. These two bits can also dis-
able the external interrupt function.
The external interrupt pin is pin-shared with the I/O pin
PA3 and can only be configured as an external interrupt
pin if the corresponding external interrupt enable bit in
the INTC0 register has been set and the edge trigger
type has been selected using the CTRL1 register. The
pin must also be setup as an input by setting the corre-
sponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and an active
transition appears on the external interrupt pin, a sub-
routine call to the external interrupt vector at location
04H, will take place. When the interrupt is serviced, the
external interrupt request flag, EIF, will be automatically
reset and the EMI bit will be automatically cleared to dis-
able other interrupts. Note that any pull-high resistor
connections on this pin will remain valid even if the pin is
used as an external interrupt input.
INTEG1
0
0
1
1
INTEG0
0
1
0
1
External interrupt disable
Rising edge Trigger
Falling edge Trigger
Both edge Trigger
Edge Trigger Type
HT45R22E
March 17, 2010
www.DataSheet4U.com