LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 14

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
General-Purpose Input/Outputs (GPIOs) ................................................................................... 169
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
14
Flash Memory Control (FMC), offset 0x008 ..................................................................... 152
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 154
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 155
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 156
USec Reload (USECRL), offset 0x140 ............................................................................ 157
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 158
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 159
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 160
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 161
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 162
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 163
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 164
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 165
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 166
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 167
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 168
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 176
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 177
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 178
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 179
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 180
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 181
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 182
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 183
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 184
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 185
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 187
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 188
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 189
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 190
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 191
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 192
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 193
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 194
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 195
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 196
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 198
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 199
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 200
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 201
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 202
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 203
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 204
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 205
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 206
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 207
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 208
Preliminary
July 25, 2008