LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 402

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Ethernet Controller
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
402
Bit/Field
31:8
7:3
2
1
0
RO
RO
31
15
0
0
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 15-2 on page 389 and in “MII Management Register
Descriptions” on page 408.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
RO
RO
30
14
0
0
REGADR
reserved
reserved
RO
RO
29
13
WRITE
START
0
0
Name
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
RO
RO
RO
26
10
0
0
Reset
0x0
0x0
0x0
0x0
0x0
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write;
otherwise, it is a read.
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR is read (WRITE=0) or written (WRITE=1).
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
REGADR
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
reserved
RO
RO
18
0
2
0
July 25, 2008
WRITE
R/W
RO
17
0
1
0
START
R/W
RO
16
0
0
0