LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 383

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

15.1
15.2
July 25, 2008
Block Diagram
Figure 15-1. Ethernet Controller Block Diagram
Functional Description
Note:
As shown in Figure 15-2 on page 383, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 15-2. Ethernet Controller
System Clock
Interrupt
Cortex M3
Stellaris® Fury-class devices incorporating an Ethernet controller should have a 12.4-kΩ
resistor connected between ERBIAS and ground to accommodate future device revisions.
The 12.4-kΩ resistor should have a 1% tolerance and should be located in close proximity
to the ERBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry
may be used.
Individual
Interrupt
Address
Support
Control
MACIACK
MACIAR0
MACIAR1
MACTSR
MACISR
MACIMR
Timer
Transmit
MACMDVR
MACMDRX
Receive
MACMDTX
Control
Control
Control
Access
MACITHR
MACMCR
MACRCR
MACNPR
MACTCR
MACTRR
MACMAR
MACDR
Data
MII
Media Access
Controller
(Layer 2)
MAC
Preliminary
Ethernet Controller
Transmit
Receive
FIFO
FIFO
Layer Entity
(Layer 1)
Physical
PHY
Media Independent Interface
Decoding
Management Register Set
Encoding
Transmit
Collision
Receive
Detect
MR0
MR1
MR2
MR3
MR16
MR17
MR4
MR5
MR6
Recovery
Shaping
Carrier
Sense
Pulse
Clock
MR18
MR19
MR23
MR24
Magnetics
LM3S6950 Microcontroller
Negotiation
Reference
MDIX
Clock
Auto
TXOP
TXON
XTLN
RJ45
XTLP
RXIP
RXIN
383