LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 91

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0010.30DF
July 25, 2008
Bit/Field
31:21
19:16
15:12
11:8
20
7
6
RO
RO
31
15
0
0
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
RO
RO
30
14
0
MINSYSDIV
0
MINSYSDIV
reserved
reserved
reserved
RO
RO
29
13
0
1
Name
PWM
MPU
HIB
RO
RO
28
12
0
1
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
reserved
Reset
0x3
RO
RO
25
0
9
0
0
1
0
0
1
1
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module Present
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
Hibernation Module Present
When set, indicates that the Hibernation module is present.
Value
0x3
MPU
RO
RO
23
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0
7
1
HIB
RO
RO
22
0
6
1
reserved
RO
RO
21
0
5
0
PWM
PLL
RO
RO
20
1
4
1
LM3S6950 Microcontroller
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
reserved
SWD
RO
RO
17
0
1
1
JTAG
RO
RO
16
0
0
1
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