LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 421

no-image

LM3S6950

Manufacturer Part Number
LM3S6950
Description
Lm3s6950 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S6950-EQC50-A2
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S6950-EQC50-A2T
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S6950-IBZ50-A2
Manufacturer:
TI
Quantity:
263
Part Number:
LM3S6950-IBZ50-A2
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S6950-IBZ50-A2T
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
LM3S6950-IQC50-A2
Manufacturer:
Texas Instruments
Quantity:
135
Part Number:
LM3S6950-IQC50-A2
Manufacturer:
ROHM
Quantity:
48 000
Part Number:
LM3S6950-IQC50-A2
Manufacturer:
Texas Instruments
Quantity:
10 000
Reset
Type
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
July 25, 2008
Bit/Field
JABBER_IE
15
14
13
12
11
10
R/W
9
8
15
0
RXER_IE
R/W
Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
14
0
ANEGCOMP_IE
JABBER_IE
RFAULT_IE
PRX_IE
LSCHG_IE
LPACK_IE
RXER_IE
R/W
PRX_IE
PDF_IE
13
0
Name
PDF_IE
R/W
12
0
LPACK_IE
R/W
11
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LSCHG_IE
R/W
10
0
RFAULT_IE
Reset
R/W
9
0
0
0
0
0
0
0
0
0
Preliminary
ANEGCOMP_IE
R/W
8
0
Description
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
Remote Fault Interrupt Enable
When set, enables system interrupts when a Remote Fault condition is
signaled by the link partner.
Auto-Negotiation Complete Interrupt Enable
When set, enables system interrupts when the Auto-Negotiation
sequence has completed successfully.
JABBER_INT
RC
7
0
RXER_INT
RC
6
0
PRX_INT
RC
5
0
PDF_INT
RC
4
0
LPACK_INT
LM3S6950 Microcontroller
RC
3
0
LSCHG_INT
RC
2
0
RFAULT_INT
RC
1
0
A N E G C O M P _ I N T
RC
0
0
421

Related parts for LM3S6950