LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 41

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
July 25, 2008
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S6950 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■
Debug
Slave
Slave
APB
ATB
Port
Port
Facilitates low-latency exception and interrupt handling
Interface
Interface
APB
ATB
®
devices have implemented TPIU as shown in Figure 2-2 on page 41.
Asynchronous FIFO
Preliminary
®
devices. This means Chapters 15 and 16 of the ARM®
(serializer)
Trace Out
LM3S6950 Microcontroller
Serial Wire
Trace Port
(SWO)
41