LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 9

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 318
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 319
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 319
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
July 25, 2008
Stellaris
CPU Block Diagram ......................................................................................................... 40
TPIU Block Diagram ........................................................................................................ 41
JTAG Module Block Diagram ............................................................................................ 51
Test Access Port State Machine ....................................................................................... 54
IDCODE Register Format ................................................................................................. 59
BYPASS Register Format ................................................................................................ 60
Boundary Scan Register Format ....................................................................................... 60
External Circuitry to Extend Reset .................................................................................... 62
Power Architecture .......................................................................................................... 65
Main Clock Tree .............................................................................................................. 67
Hibernation Module Block Diagram ................................................................................. 126
Clock Source Using Crystal ............................................................................................ 127
Clock Source Using Dedicated Oscillator ......................................................................... 128
Flash Block Diagram ...................................................................................................... 145
GPIO Port Block Diagram ............................................................................................... 170
GPIODATA Write Example ............................................................................................. 171
GPIODATA Read Example ............................................................................................. 171
GPTM Module Block Diagram ........................................................................................ 211
16-Bit Input Edge Count Mode Example .......................................................................... 215
16-Bit Input Edge Time Mode Example ........................................................................... 216
16-Bit PWM Mode Example ............................................................................................ 217
WDT Module Block Diagram .......................................................................................... 246
UART Module Block Diagram ......................................................................................... 270
UART Character Frame ................................................................................................. 271
IrDA Data Modulation ..................................................................................................... 273
SSI Module Block Diagram ............................................................................................. 310
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 313
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 313
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 314
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 314
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 315
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 316
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 316
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 317
I
I
START and STOP Conditions ......................................................................................... 348
Complete Data Transfer with a 7-Bit Address ................................................................... 349
R/S Bit in First Byte ........................................................................................................ 349
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 352
2
2
C Block Diagram ......................................................................................................... 347
C Bus Configuration .................................................................................................... 348
®
6000 Series High-Level Block Diagram ............................................................... 32
Preliminary
2
C Bus ............................................................... 349
LM3S6950 Microcontroller
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