LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 474

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
474
Bit/Field
31:12
11:0
RO
RO
31
15
0
0
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge
delayed.
RO
RO
30
14
0
0
reserved
RiseDelay
reserved
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
RO
R/W
RO
26
10
0
0
Reset
0x00
R/W
RO
25
0
9
0
0
Preliminary
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
RiseDelay
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
July 25, 2008
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0