LM3S6950 Luminary Micro, Inc, LM3S6950 Datasheet - Page 423

• Manufacturer Part Number: LM3S6950
• Description: Lm3s6950 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
July 25, 2008
Bit/Field
15:13
7:0
12
11
10
9
8
RO
15
0
reserved
Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous Auto-Negotiation.
RO
14
0
RX_LOCK
reserved
reserved
RO
ANEGF
13
0
Name
RXSD
DPLX
RATE
ANEGF
RC
12
0
DPLX
RO
11
0
Type
RO
RO
RO
RO
RO
RO
RC
RATE
RO
10
0
Reset
RXSD
RO
00
9
0
0
0
0
0
0
0
Preliminary
RX_LOCK
RO
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto-Negotiation Failure
When set, indicates that no common technology was found during
Auto-Negotiation and has failed. This bit remains set until read.
Duplex Mode
When set, indicates that Full-Duplex was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
Rate
When set, indicates that 100Base-TX was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
10Base-TX was the highest common denominator found.
Receive Detection
When set, indicates that receive signal detection has occurred (in
100Base-TX mode) or that Manchester-encoded data has been detected
(in 10Base-T mode).
Receive PLL Lock
When set, indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or 100Base-TX).
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
7
0
RO
6
0
RO
5
0
RO
4
0
reserved
LM3S6950 Microcontroller
RO
3
0
RO
2
0
RO
1
0
RO
0
0
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