adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 14

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
Table 6. Pin List (Continued)
1
2
Name
TCK
TRST
EMU
CLK_CFG
BOOT_CFG
RESET
XTAL
CLKIN
CLKOUT/
RESETOUT/
RUNRSTIN
BR
RPBA
ID
Pull-up/pull-down resistor can not be enabled/disabled and the value of the pull-up/pull-down resistor cannot be programmed.
Range of fixed pull-up resistor can be between 26k-63k . Range of fixed pull-down resistor can be between 31k-85k .
2-0
6-1
1–0
2–0
Type
I (pu)
I (pu)
O/T (pu)
I
I
I (pu)
O
I
I/O (pu)
I/O
I
I
LVTTL SSTL18
Rev. PrB | Page 14 of 56 | November 2008
State
During
and After
Reset
High-Z
High-Z/
Driven low
Description
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be
asserted (pulsed low) after power-up or held low for proper operation of the
ADSP-21469.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-
21469. TRST has a fixed internal pull-up resistor
Emulation Status. Must be connected to the ADSP-21469 Analog Devices
DSP Tools product line of JTAG emulators target board connector only. EMU
has a fixed internal pull-up resistor
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See
Table 9
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes
out of reset.
Boot Configuration Select. These pins select the boot mode for the proces-
sor. The BOOTCFG pins must be valid before reset is asserted. See
a description of the boot modes.
Processor Reset. Resets the ADSP-21469 to a known state. Upon deassertion,
there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core
begins program execution from the hardware reset vector address. The RESET
input must be asserted (low) at power-up.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an
external crystal.
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21469 clock
input. It configures the ADSP-21469 to use either its internal clock generator
or an external clock source. Connecting the necessary components to CLKIN
and XTAL enables the internal clock generator. Connecting the external clock
to CLKIN while leaving XTAL unconnected configures the ADSP-21469 to use
the external clock source such as an external clock oscillator. CLKIN may not
be halted, changed, or operated below the specified frequency.
Clock Out/Reset Out/Running Reset In. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTL
register. The default is reset out. This pin also has a third function as RUNRSTIN.
The functionality of which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-2146x SHARC Processor Hardware
Reference.
Bus request. Bus request pins for external DDR2 bus arbitration.
Rotating priority bus arbitration.
Chip ID
for a description of the clock configuration modes.
Preliminary Technical Data
1, 2
.
1, 2
.
Table 8
for