adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 45

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SPI Interface—Master
The ADSP-21469 contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 42
Table 42. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
and
Table 43
FLAG3
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
SPICLK
(CP = 0)
SPICLK
(CP = 1)
MOSI
(INPUT)
MOSI
(INPUT)
MISO
MISO
-
0
applies to both.
Data Input Valid To SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge To Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
t
SS PIDM
t
SDSCIM
VALID
MSB
t
t
MSB
SPICHM
SPICL M
VALID
MSB
t
HSPIDM
t
t
Rev. PrB | Page 45 of 56 | November 2008
D DSPIDM
t
SSPIDM
t
MSB
SPICLM
SPICHM
Figure 34. SPI Master Timing
t
DDSPIDM
t
HSPIDM
t
HDSPIDM
t
t
SS PIDM
HDSPIDM
t
VALID
SPI CLKM
LSB
LSB
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
VALID
LSB
ADSP-21469/ADSP-21469W
t
HDSM
LSB
t
HS PIDM
t
SPIT DM
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns