adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 37

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Input Data Port (IDP)
The timing requirements for the IDP are given in
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro-
vided below are valid at the DAI_P20–1 pins.
Table 34. Input Data Port (IDP)
1
Sample Rate Converter—Serial Input Port
The ASRC input signals (SCLK, FS, and SDATA) are routed
from the DAI_P20–1 pins using the SRU. Therefore, the timing
specifications provided in
pins.
Table 35. ASRC, Serial Input Port
1
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
1
1
1
1
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
Table 35
are valid at the DAI_P20–1
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
-
-
-
1
1
1
Rev. PrB | Page 37 of 56 | November 2008
Table
Figure 24. IDP Master Timing
34. IDP
t
IPDCLKW
t
SISFS
t
SISD
SAMPLE EDGE
t
IPDCLK
t
SIHFS
t
SIHD
Min
TBD
TBD
TBD
TBD
TBD
TBD
Min
TBD
TBD
TBD
TBD
TBD
TBD
ADSP-21469/ADSP-21469W
Max
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns