adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 35

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 32. Serial Ports—Enable and Three-State
1
Table 33. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
1
1
1
1
1
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20
THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES
ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.
DAI_P20 - 1
DAI_P20 - 1
(SCLK)
(SCLK)
(FS)
(FS)
DRIVE
DRIVE
t
DDTLFSE
t
D DTLFSE
t
Rev. PrB | Page 35 of 56 | November 2008
t
SFSE/I
SFSE/I
t
DDTENFS
Figure 22. External Late Frame Sync
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DDTENFS
LATE EXTERNAL TRANSMIT FS
SAMPLE
SAMPLE
DATA CHANNEL
1ST BIT
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
t
A/B) ARE ROUTED TO THE DAI_P20
HFSE/I
t
HFSE/I
1
Min
TBD
TBD
TBD
Min
TBD
TBD
t
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
ADSP-21469/ADSP-21469W
-
-
1 PINS.
Max
Max
TBD
TBD
TBD
TBD
TBD
1 PINS
Unit
ns
ns
ns
Unit
ns
ns