adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 44

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the TBD × FS clock.
Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is TBD x FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
(DATA CHANNEL A/B)
DAI_P20-1
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20-1
DAI_P20-1
(SCLK)
(FS)
Rev. PrB | Page 44 of 56 | November 2008
DRIVE EDGE
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
Min
TBD
TBD
TBD
TBD
TBD
SAMPLE EDGE
Max
TBD
TBD
TBD
TBD
TBD
Preliminary Technical Data
Unit
ns
ns
ns
ns
ns