adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 4

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
GENERAL DESCRIPTION
The ADSP-21469 SHARC
SHARC family of DSPs that feature Analog Devices' Super Har-
vard Architecture. The ADSP-21469 is source code compatible
with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-
2116x DSPs as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The ADSP-21469 is a 32-bit/40-bit floating point proces-
sors optimized for high performance audio applications with its
large on-chip SRAM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
Table 1. SHARC Features
As shown in the functional block diagram
ADSP-21469 uses two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21469 processor achieves
an instruction cycle time of 2.22 ns at 450 MHz. With its SIMD
computational hardware, the ADSP-21469 can perform
2.7 GFLOPS.
Feature
Frequency
Core
Internal RAM
DDR2 Memory Interface
DDR2 Memory Bus Width
Direct DMA from SPORTs to external
memory
FFT accelerator
FIR accelerator
IIR accelerator
IDP
Serial Ports
ASRC (channels)
UART
DAI and DPI
Link Ports
S/PDIF transceiver
AMI interface with 8-bit support
SPI
TWI
Package
®
processor is a member of the SIMD
Description
450 MHz
5-stage pipeline
5 Mbits
1/2 CCLK Max
16-bits
Yes
Yes
Yes
Yes
Yes
8
8
1
20/14 pins
2
1
Yes
2
1
324-ball,
19 mm x 19 mm PBGA
on Page
Rev. PrB | Page 4 of 56 | November 2008
1, the
Table 2
Table 2. Processor Benchmarks
1
The ADSP-21469 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21469
following architectural features:
The block diagram of the ADSP-21469
the following architectural features:
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal) 20.44 s
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
Divide (y/×)
Inverse Square Root
Assumes two files in multichannel SIMD mode
• Two processing elements, each of which comprises an
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Two programmable interval timers with external event
• On-chip SRAM
• JTAG test access port
• DMA controller
• Digital applications interface that includes four precision
• Digital peripheral interface that includes two timers, one
ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
counter capabilities
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter with four independent asyn-
chronous sample rate converters, an input data port (IDP)
with eight serial ports, eight serial interfaces, a 20-bit paral-
lel input port (PDAP), and a flexible signal routing unit
(DAI SRU).
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
shows performance benchmarks for the ADSP-21469.
Preliminary Technical Data
1
1
on Page 1
on Page 1
Speed
(at 450 MHz)
1.11 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
10.0 ns
also illustrates
illustrates the