adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 48

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
TWI Controller Timing
Table 45
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices
1
Parameter
f
t
t
t
t
t
t
t
t
t
All values referred to V
SCL
HDSTA
LOW
HIGH
SUSTA
HDDAT
SUDAT
SUSTO
BUF
SP
DPI_P14-1
DPI_P14-1
SDA
SCL
and
Figure 37
SCL Clock Frequency
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated Start Condition
Data Hold Time for TWI-bus Devices
Data Setup Time
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Spikes Suppressed By the Input Filter n/a
S
IHmin
provide timing information for the TWI
and V
t
t
LOW
HDS TA
ILmax
levels.
t
For more information, see Electrical Characteristics on page 17.
H DDA T
Figure 37. Fast and Standard Mode Timing on the TWI Bus
Rev. PrB | Page 48 of 56 | November 2008
t
HIGH
t
SUDA T
t
SUS TA
Standard Mode
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Sr
t
HDS TA
Max
TBD
n/a
Preliminary Technical Data
1
t
SP
t
Fast Mode
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
SUSTO
P
t
Max
TBD
TBD
BUF
S
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns