adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 9

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
and Synchronous/Asynchronous Sample Rate Converter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
right justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The sample rate converter (ASRC) contains four ASRC blocks
and is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The ASRC block is used to perform synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con-
vert multichannel audio data without phase mismatches.
Finally, the ASRC can be used to clean up audio data from jit-
tery clock sources such as the S/PDIF receiver.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral (Compatible) Interface
The ADSP-21469 SHARC processor contains two serial periph-
eral interface ports (SPIs). The SPI is an industry-standard
synchronous serial link, enabling the ADSP-21469 SPI-compat-
ible port to communicate with other SPI compatible devices.
The SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup-
porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI-compatible devices, either acting as a master or slave
device. The ADSP-21469 SPI-compatible peripheral implemen-
tation also features programmable baud rate and clock phase
and polarities. The ADSP-21469 SPI-compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
UART Port
The ADSP-21469 processor provides a full-duplex Universal
Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
Rev. PrB | Page 9 of 56 | November 2008
2
S or
transfers of serial data. The UART also has multiprocessor com-
munication capability using 9-bit address detection. This allows
it to be used in multidrop networks through the RS-485 data
interface standard. The UART port also includes support for 5
to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Timers
The ADSP-21469 has a total of three timers: a core timer that
can generate periodic software interrupts and two general pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables both general-
purpose timers independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I
The TWI master incorporates the following features:
• PIO (programmed I/O) – The processor sends or receives
• DMA (direct memory access) – The DMA controller trans-
• Supporting bit rates ranging from (f
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
• 7-bit addressing
• Simultaneous master and slave operation on multiple
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
device systems with support for multi master data
arbitration
PCLK
/16) bits per second.
ADSP-21469/ADSP-21469W
PCLK
/ 1,048,576) to
2
C bus protocol.