adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 40

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2146x SHARC Processor Hardware
Table 37. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Source pins of AMI_DATA are DATA7–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SPCLKEN
HPCLKEN
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
1
1
37. PDAP is the parallel mode operation of Channel 0 of
1
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
(PDAP_STROBE)
(PDAP_CLKEN)
DAI_P20
DAI_P20
(PDAP_CLK)
DAI_P20
DATA
-
-
1
-
1
1
Rev. PrB | Page 40 of 56 | November 2008
Figure 27. PDAP Timing
t
PDCLKW
SAMPLE EDGE
t
SPCLKEN
t
PDSD
t
PDHLDD
Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA7-0 pins. The
remaining four bits can only be sourced through DAI_P4–1.
The timing below is valid at the DATA7–0 pins.
t
PDCLK
t
HPCLKEN
t
PDHD
t
PDSTRB
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
ns
ns