z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 115

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

100
UM005003-0703
DM1 DM0 SM1 SM0 Transfer Mode
1
1
1
1
Note: *: includes memory mapped I/O.
Z8018x
Family MPU User Manual
1
1
1
1
0
0
1
1
Table 14.
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of Wait States into DMAC (and CPU)
accesses of memory or I/O Also, the DMA request mode for each DREQ
DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
0
1
0
1
Memory
Memory
Reserved
Reserved
Transfer Mode Combinations
to
to
I/O
I/O
Increment/Decrement
SAR0+1, DAR0 fixed
SAR0-1, DAR0 fixed