z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 117
z80189
Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80189.pdf
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102
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
7
6
5
3
–
Z8018x
Family MPU User Manual
4
Reserved
7
R/W
0
Table 15.
DIM1 DIM0 Transfer Mode
0
0
1
1
6
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
Channel 1 Transfer Mode
Value Description
5
0
1
0
0
1
Memory
Memory
I/O
I/O
to
to
Reserved
Alternating Channels
DMA Channels are independent
Toggle between DMA channels for same device
Currently selected DMA channel when Bit 7 = 1
Reserved. Must be 0.
TOUT/DREQ is DREQ In
TOUT/DREQ is TOUT Out
R/W
Memory
Memory
0
to
to
4
I/O
I/O
3
R/W
0
Address Increment/Decrement
MARI +1, IAR1 fixed
MARI -1, IAR1 fixed
IAR1 fixed, MAR1+1
IAR1 fixed, MAR1-1
2
1
R/W
0
0
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