z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 86

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

A0
D0
MREQ
–
–
A19
WR
Phi
RD
D7
MI
stacked PC-1. If UFO is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Figure 32.
T1
2nd Op Code
Fetch Cycle
T2
Undefined
Op Code
T3
TRAP Timing Diagram -2nd Op Code Undefined
PC
Ti
Ti
Ti
1
, the starting address of the invalid instruction is
Ti
Ti
T1
T2
SP-1
PCH
PC Stacking
T3
Family MPU User Manual
T1
T2
SP-2
PCL
T3
Restart from 0000H
UM005003-0703
T1
Op Code
Fetch Cycle
T2
0000H
Z8018x
T3
71