z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 59

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

44
Table 6.
UM005003-0703
ASCI
CSI/O CSI/O Control Register
Z8018x
Family MPU User Manual
Register
ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
CSI/O Transmit/Receive Data Register TRD
I/O Address Map for Z80180-Class Processors Only
address to
OTDMR and TSTIO (see Instruction Set).
When writing to an internal I/O register, the same I/O write occurs on the
external bus. However, the duplicate external I/O write cycle exhibits
internal I/O write cycle timing. For example, the WAIT input and
programmable Wait State generator are ignored. Similarly, internal I/O
read cycles also cause a duplicate external I/O read cycle. However, the
external read data is ignored by the Z8X180.
Normally, external I/O addresses should be chosen to avoid overlap with
internal I/O addresses and duplicate I/O accesses.
0
. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM,
STAT0
STAT1
TDR0
CNTR
CNTLA0
CNTLA1
CNTLB0
CNTLB1
TDR1
RDR0
RDR1
Mnemonic
XX000000
XX000001
XX000010
XX000100
XX000101
XX001010
XX000011
XX000110
XX000111
XX001000
XX001001
XX1011
Binary
Address
0AH
0BH
Hex
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
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