z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 97

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

82
UM005003-0703
Interrupt Source
INT1
INT2
PRT channel 0
PRT channel 1
DMA channel 0
DMA channel 1
CSI/O
ASCI channel 0
ASCI channel 1
Z8018x
Family MPU User Manual
Interrupt Acknowledge Cycle Timings
individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower
vector of INT1 INT2 and internal interrupt are summarized in Table 9.
Table 9.
Figure 43 illustrates INT1, INT2, and internal interrupts timing. INT1 and
INT2 are sampled at the falling edge of the clock state prior to T2 or T1 in
the last machine cycle. If INT1 or INT2 is asserted Low at the falling
edge of clock state prior to T3 or T1 in the last machine cycle, the
interrupt request is accepted.
Priority
Highest
Lowest
Vector Table
—
—
—
—
—
—
IL
b7
—
—
—
b6
—
—
—
—
—
—
—
—
—
b5
—
—
—
—
—
—
—
—
—
Fixed Code
b4
0
0
0
0
0
0
0
0
1
b3
0
0
0
0
1
1
1
1
0
b2
0
0
1
1
0
0
1
1
0
b1
0
1
0
1
0
1
0
1
0
b0
0
0
0
0
0
0
0
0
0