z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 50

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

INT1, NMI
A0
Figure 21.
IOSTOP Mode
IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to
operating. However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to
SYSTEM STOP Mode
SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes.
SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to
followed by execution of the SLP instruction. In this mode, on-chip I/O
and CPU stop operating, reducing power consumption. Recovery from
SYSTEM STOP mode is the same as recovery from SLEEP mode, noting
that internal I/O sources, (disabled by IOSTOP) cannot generate a
recovery interrupt.
Phi
HALT
M1
–
A19
SLP 2nd Op Code
Fetch Cycle
T2
SLP 2nd Op Code address
SLEEP Timing Diagram
T3
1
. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops
T1
T2
SLEEP mode
TS
FFFFFH
Family MPU User Manual
TS
T1
Op Code Fetch or Interrupt
Acknowledge Cycle
T2
0
UM005003-0703
.
Z8018x
T3
1
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