mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 149

• Manufacturer Part Number: mc68hc908gp32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

13.8.3 SCI Control Register 3
SCI control register 3:
R8 — Received Bit 8
T8 — Transmitted Bit 8
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
Freescale Semiconductor
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When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE.
(See
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables these interrupts:
–
–
–
Parity error interrupts
13.8.4 SCI Status Register
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
Address:
Reset:
Read:
Write:
$0015
Bit 7
R8
U
Figure 13-11. SCI Control Register 3 (SCC3)
= Unimplemented
T8
U
6
MC68HC908GP32 Data Sheet, Rev. 10
1.) Reset clears PEIE.
R
5
0
R = Reserved
R
4
0
ORIE
3
0
NEIE
U = Unaffected
2
0
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
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