mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 227

• Manufacturer Part Number: mc68hc908gp32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

18.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
18.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
18.3.1.6 Baud Rate
The communication baud rate is controlled by the external clock and the state of the PTC3 pin (when IRQ
is set to V
V
Table 18-1
baud rate is the bus frequency divided by 256.
18.3.1.7 Commands
The monitor ROM firmware uses these commands:
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
Freescale Semiconductor
DD
•
•
•
•
•
•
or V
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
SS
TST
lists external frequencies required to achieve a standard baud rate of 9600 bps. The effective
on IRQ, then the baud rate is independent of PTC3.
) upon entry into monitor mode. If monitor mode was entered with a blank reset vector and
Wait one bit time after each echo before sending the next byte.
START
BIT
0
BIT 0
1
2
MISSING STOP BIT
BIT 1
3
Figure 18-12. Monitor Data Format
Figure 18-13. Break Transaction
4
MC68HC908GP32 Data Sheet, Rev. 10
BIT 2
5
6
BIT 3
7
BIT 4
NOTE
BIT 5
2-STOP BIT DELAY BEFORE ZERO ECHO
BIT 6
0
1
BIT 7
2
3
STOP
BIT
4
START
NEXT
5
BIT
6
Monitor Module (MON)
7
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