mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 86

• Manufacturer Part Number: mc68hc908gp32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 8176 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period
of 250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12 through 5 of the prescaler.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at V
V
7.3 I/O Signals
The following paragraphs describe the signals shown in
7.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
7.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
7.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low
byte of the reset vector.
7.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
7.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
7.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
86
TST
on the RST pin disables the COP.
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908GP32 Data Sheet, Rev. 10
NOTE
NOTE
Figure
7.4 COP Control
7-1.
TST
. During the break state,
Register) clears the COP
Freescale Semiconductor