mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 115

• Manufacturer Part Number: mc68hc11f1cpu3
• Description: Mc68hc11f1 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

OC1M — Output Compare 1 Mask
OC1M[7:3] — Output Compare Masks
Bits [2:0] — Not implemented
9.3.4 Output Compare Data Register
OC1D — Output Compare 1 Data
Bits [2:0] — Not implemented
9.3.5 Timer Counter Register
TCNT — Timer Counter
9.3.6 Timer Control Register 1
TECHNICAL DATA
$100E
RESET:
RESET:
$100F
Always read zero
Use this register with OC1 to specify the data that is to be stored on the affected pin
of port A after a successful OC1 compare. When a successful OC1 compare occurs,
a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in
OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Always read zero
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A
full counter read addresses the most significant byte (MSB) first. A read of this address
causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-
cle so that a double-byte read returns the full 16-bit state of the counter at the time of
the MSB read cycle.
TCNT resets to $0000. In normal modes, TCNT is a read-only register.
The bits of this register specify the action taken as a result of a successful OCx com-
pare.
0 = OC1 is disabled.
1 = OC1 is enabled to control the corresponding pin of port A
Bit 15
Bit 7
OC1M7
OC1D7
Bit 7
Bit 7
0
0
14
6
OC1M6
OC1D6
6
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
13
5
OC1M5
OC1D5
5
0
5
0
Go to: www.freescale.com
12
4
TIMING SYSTEM
OC1M4
OC1D4
4
0
4
0
11
3
OC1M3
OC1D3
0
0
3
3
10
2
—
—
2
0
2
0
9
1
—
—
1
0
1
0
Bit 8
Bit 0
Bit 0
Bit 0
$100E, $100F
—
—
0
0
TCNT (High)
TCNT (Low)
$100C
$100D
9-9